Assignee
ATOMERA INC
US·109 granted patents·49 pending applications·2,913 citations·filing 2014–2025
Top patents by PatentIndex Score
158 records- 0199US11978771B2Gate-all-around (GAA) device including a superlatticeATOMERA INC·Filed 2022·Granted May 7, 2024·7 cites·21 claims
- 0299US11848356B2Method for making semiconductor device including superlattice with oxygen and carbon monolayersATOMERA INC·Filed 2021·Granted Dec 19, 2023·6 cites·21 claims
- 0399US11837634B2Semiconductor device including superlattice with oxygen and carbon monolayersATOMERA INC·Filed 2021·Granted Dec 5, 2023·10 cites·21 claims
- 0499US11742202B2Methods for making radio frequency (RF) semiconductor devices including a ground plane layer having a superlatticeATOMERA INC·Filed 2022·Granted Aug 29, 2023·10 cites·23 claims
- 0599US11728385B2Semiconductor device including superlattice with O18 enriched monolayersATOMERA INC·Filed 2021·Granted Aug 15, 2023·7 cites·24 claims
- 0699US11721546B2Method for making semiconductor device with selective etching of superlattice to accumulate non-semiconductor atomsATOMERA INC·Filed 2021·Granted Aug 8, 2023·6 cites·20 claims
- 0799US11430869B2Method for making superlattice structures with reduced defect densitiesATOMERA INC·Filed 2020·Granted Aug 30, 2022·8 cites·13 claims
- 0899US10593761B1Method for making a semiconductor device having reduced contact resistanceATOMERA INC·Filed 2018·Granted Mar 17, 2020·51 cites·21 claims
- 0999US10580866B1Semiconductor device including source/drain dopant diffusion blocking superlattices to reduce contact resistanceATOMERA INC·Filed 2018·Granted Mar 3, 2020·49 cites·21 claims
- 1099US10453945B2Semiconductor device including resonant tunneling diode structure having a superlatticeATOMERA INC·Filed 2017·Granted Oct 22, 2019·45 cites·23 claims
- 1199US10361243B2Method for making CMOS image sensor including superlattice to enhance infrared light absorptionATOMERA INC·Filed 2017·Granted Jul 23, 2019·44 cites·20 claims
- 1299US10276625B1CMOS image sensor including superlattice to enhance infrared light absorptionATOMERA INC·Filed 2017·Granted Apr 30, 2019·54 cites·20 claims
- 1399US10249745B2Method for making a semiconductor device including a resonant tunneling diode structure having a superlatticeATOMERA INC·Filed 2017·Granted Apr 2, 2019·52 cites·22 claims
- 1499US10191105B2Method for making a semiconductor device including threshold voltage measurement circuitryATOMERA INC·Filed 2017·Granted Jan 29, 2019·62 cites·20 claims
- 1599US10170560B2Semiconductor devices with enhanced deterministic doping and related methodsATOMERA INC·Filed 2017·Granted Jan 1, 2019·60 cites·21 claims
- 1699US10170604B2Method for making a semiconductor device including a resonant tunneling diode with electron mean free path control layersATOMERA INC·Filed 2017·Granted Jan 1, 2019·60 cites·20 claims
- 1799US10170603B2Semiconductor device including a resonant tunneling diode structure with electron mean free path control layersATOMERA INC·Filed 2017·Granted Jan 1, 2019·61 cites·20 claims
- 1899US10107854B2Semiconductor device including threshold voltage measurement circuitryATOMERA INC·Filed 2017·Granted Oct 23, 2018·70 cites·21 claims
- 1999US10109479B1Method of making a semiconductor device with a buried insulating layer formed by annealing a superlatticeATOMERA INC·Filed 2017·Granted Oct 23, 2018·82 cites·23 claims
- 2099US10109342B2Dram architecture to reduce row activation circuitry power and peripheral leakage and related methodsATOMERA INC·Filed 2017·Granted Oct 23, 2018·74 cites·23 claims
- 2199US9941359B2Semiconductor devices with superlattice and punch-through stop (PTS) layers at different depths and related methodsATOMERA INC·Filed 2016·Granted Apr 10, 2018·73 cites·23 claims
- 2299US9899479B2Semiconductor devices with superlattice layers providing halo implant peak confinement and related methodsATOMERA INC·Filed 2016·Granted Feb 20, 2018·89 cites·21 claims
- 2398US11935940B2Methods for making bipolar junction transistors including emitter-base and base-collector superlatticesATOMERA INC·Filed 2022·Granted Mar 19, 2024·6 cites·6 claims
- 2498US11923431B2Bipolar junction transistors including emitter-base and base-collector superlatticesATOMERA INC·Filed 2022·Granted Mar 5, 2024·6 cites·8 claims
- 2598US11923418B2Semiconductor device including a superlattice and enriched silicon 28 epitaxial layerATOMERA INC·Filed 2021·Granted Mar 5, 2024·7 cites·24 claims
- 2698US11869968B2Semiconductor device including a superlattice and an asymmetric channel and related methodsATOMERA INC·Filed 2022·Granted Jan 9, 2024·8 cites·17 claims
- 2798US11810784B2Method for making semiconductor device including a superlattice and enriched silicon 28 epitaxial layerATOMERA INC·Filed 2021·Granted Nov 7, 2023·9 cites·27 claims
- 2898US11682712B2Method for making semiconductor device including superlattice with O18 enriched monolayersATOMERA INC·Filed 2021·Granted Jun 20, 2023·7 cites·24 claims
- 2998US11664427B2Vertical semiconductor device with enhanced contact structure and associated methodsATOMERA INC·Filed 2022·Granted May 30, 2023·7 cites·32 claims
- 3098US11631584B1Method for making semiconductor device with selective etching of superlattice to define etch stop layerATOMERA INC·Filed 2021·Granted Apr 18, 2023·7 cites·20 claims
- 3198US11437487B2Bipolar junction transistors including emitter-base and base-collector superlatticesATOMERA INC·Filed 2020·Granted Sep 6, 2022·8 cites·11 claims
- 3298US11437486B2Methods for making bipolar junction transistors including emitter-base and base-collector superlatticesATOMERA INC·Filed 2020·Granted Sep 6, 2022·8 cites·11 claims
- 3398US11387325B2Vertical semiconductor device with enhanced contact structure and associated methodsATOMERA INC·Filed 2020·Granted Jul 12, 2022·12 cites·35 claims
- 3498US11329154B2Semiconductor device including a superlattice and an asymmetric channel and related methodsATOMERA INC·Filed 2020·Granted May 10, 2022·14 cites·18 claims
- 3598US11302823B2Method for making semiconductor device including a superlattice with different non-semiconductor material monolayersATOMERA INC·Filed 2020·Granted Apr 12, 2022·11 cites·21 claims
- 3698US11177351B2Semiconductor device including a superlattice with different non-semiconductor material monolayersATOMERA INC·Filed 2020·Granted Nov 16, 2021·16 cites·21 claims
- 3798US11094818B2Method for making a semiconductor device including a superlattice and an asymmetric channel and related methodsATOMERA INC·Filed 2020·Granted Aug 17, 2021·18 cites·23 claims
- 3898US11075078B1Method for making a semiconductor device including a superlattice within a recessed etchATOMERA INC·Filed 2020·Granted Jul 27, 2021·21 cites·24 claims
- 3998US10884185B2Semiconductor device including vertically integrated optical and electronic devices and comprising a superlatticeATOMERA INC·Filed 2019·Granted Jan 5, 2021·19 cites·20 claims
- 4098US10879356B2Method for making a semiconductor device including enhanced contact structures having a superlatticeATOMERA INC·Filed 2019·Granted Dec 29, 2020·21 cites·26 claims
- 4198US10868120B1Method for making a varactor with hyper-abrupt junction region including a superlatticeATOMERA INC·Filed 2019·Granted Dec 15, 2020·31 cites·25 claims
- 4298US10854717B2Method for making a FINFET including source and drain dopant diffusion blocking superlattices to reduce contact resistanceATOMERA INC·Filed 2018·Granted Dec 1, 2020·32 cites·20 claims
- 4398US10847618B2Semiconductor device including body contact dopant diffusion blocking superlattice having reduced contact resistanceATOMERA INC·Filed 2018·Granted Nov 24, 2020·33 cites·20 claims
- 4498US10840337B2Method for making a FINFET having reduced contact resistanceATOMERA INC·Filed 2018·Granted Nov 17, 2020·31 cites·21 claims
- 4598US10840336B2Semiconductor device with metal-semiconductor contacts including oxygen insertion layer to constrain dopants and related methodsATOMERA INC·Filed 2018·Granted Nov 17, 2020·31 cites·17 claims
- 4698US10840335B2Method for making semiconductor device including body contact dopant diffusion blocking superlattice to reduce contact resistanceATOMERA INC·Filed 2018·Granted Nov 17, 2020·31 cites·23 claims
- 4798US10840388B1Varactor with hyper-abrupt junction region including a superlatticeATOMERA INC·Filed 2019·Granted Nov 17, 2020·33 cites·23 claims
- 4898US10825901B1Semiconductor devices including hyper-abrupt junction region including a superlatticeATOMERA INC·Filed 2019·Granted Nov 3, 2020·32 cites·17 claims
- 4998US10825902B1Varactor with hyper-abrupt junction region including spaced-apart superlatticesATOMERA INC·Filed 2019·Granted Nov 3, 2020·30 cites·22 claims
- 5098US10818755B2Method for making semiconductor device including source/drain dopant diffusion blocking superlattices to reduce contact resistanceATOMERA INC·Filed 2018·Granted Oct 27, 2020·33 cites·21 claims
Showing the top 50 of 158 patent records by PatentIndex Score.
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