Assignee
AVERY DESIGN SYSTEMS INC
US·9 granted patents·19 citations·filing 2014–2020
Top patents by PatentIndex Score
9 records- 0184US11263376B1System and method for fixing unknowns when simulating nested clock gatersAVERY DESIGN SYSTEMS INC·Filed 2020·Granted Mar 1, 2022·2 cites·17 claims
- 0283US11321507B1System and method for accurate X handling using logic and symbolic cosimulationAVERY DESIGN SYSTEMS INC·Filed 2020·Granted May 3, 2022·2 cites·19 claims
- 0381US10852354B1System and method for accelerating real X detection in gate-level logic simulationAVERY DESIGN SYSTEMS INC·Filed 2019·Granted Dec 1, 2020·3 cites·19 claims
- 0479US10740521B1System and method for localized logic simulation replay using emulated valuesAVERY DESIGN SYSTEMS INC·Filed 2019·Granted Aug 11, 2020·3 cites·15 claims
- 0574US9058452B1Systems and methods for tracing and fixing unknowns in gate-level simulationAVERY DESIGN SYSTEMS INC·Filed 2014·Granted Jun 16, 2015·4 cites·9 claims
- 0669US10666255B1System and method for compacting X-pessimism fixes for gate-level logic simulationAVERY DESIGN SYSTEMS INC·Filed 2017·Granted May 26, 2020·2 cites·10 claims
- 0768US10726180B1Systems and methods for fixing X-pessimism from uninitialized latches in gate-level simulationAVERY DESIGN SYSTEMS INC·Filed 2019·Granted Jul 28, 2020·1 cites·15 claims
- 0861US10794954B1System and method for accelerating timing-accurate gate-level logic simulationAVERY DESIGN SYSTEMS INC·Filed 2019·Granted Oct 6, 2020·1 cites·18 claims
- 0959US8938705B1Systems and methods for partial retention synthesisAVERY DESIGN SYSTEMS INC·Filed 2014·Granted Jan 20, 2015·1 cites·11 claims
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