Assignee
BARTLEY GERALD KEITH
US·3 granted patents·4 pending applications·16 citations·filing 2007–2010
Top patents by PatentIndex Score
7 records- 0183US8519304B2Implementing selective rework for chip stacks and silicon carrier assembliesBARTLEY GERALD KEITH·Filed 2010·Granted Aug 27, 2013·6 cites·9 claims
- 0273US8108647B2Digital data architecture employing redundant links in a daisy chain of component modulesBARTLEY GERALD KEITH·Filed 2009·Granted Jan 31, 2012·6 cites·20 claims
- 0368US8174103B2Enhanced architectural interconnect options enabled with flipped die on a multi-chip packageBARTLEY GERALD KEITH·Filed 2008·Granted May 8, 2012·4 cites·1 claims
- 0447US2009300411A1Implementing Redundant Memory Access Using Multiple Controllers for Memory SystemBARTLEY GERALD KEITH·Filed 2008·Application pending·0 cites
- 0547US2009300291A1Implementing Cache Coherency and Reduced Latency Using Multiple Controllers for Memory SystemBARTLEY GERALD KEITH·Filed 2008·Application pending·0 cites
- 0645US2009006774A1High Capacity Memory Subsystem Architecture Employing Multiple-Speed BusBARTLEY GERALD KEITH·Filed 2007·Application pending·0 cites
- 0744US2008178136A1Method, Apparatus, and Computer Program Product for Implementing Balanced Wiring Delay Within an Electronic PackageBARTLEY GERALD KEITH·Filed 2007·Application pending·0 cites
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