Assignee
BERKOVITZ ASHER
IL·4 granted patents·6 citations·filing 2011–2013
Top patents by PatentIndex Score
4 records- 0165US9171117B2Method for ranking paths for power optimization of an integrated circuit design and corresponding computer program productBERKOVITZ ASHER·Filed 2011·Granted Oct 27, 2015·3 cites·20 claims
- 0264US9836567B2Method of simulating a semiconductor integrated circuit, computer program product, and device for simulating a semiconductor integrated circuitBERKOVITZ ASHER·Filed 2012·Granted Dec 5, 2017·3 cites·19 claims
- 0347US9607117B2Method and apparatus for calculating delay timing values for an integrated circuit designBERKOVITZ ASHER·Filed 2013·Granted Mar 28, 2017·0 cites·13 claims
- 0435US9792399B2Integrated circuit hierarchical design tool apparatus and method of hierarchically designing an integrated circuitBERKOVITZ ASHER·Filed 2013·Granted Oct 17, 2017·0 cites·15 claims
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