Assignee
CADENCE DESIGN SYSTEMS INC
US·2,021 granted patents·27 pending applications·32,689 citations·filing 1991–2024
Top patents by PatentIndex Score
2,048 records- 0199US8957802B1Metastability error detection and correction system and method for successive approximation analog-to-digital convertersCADENCE DESIGN SYSTEMS INC·Filed 2013·Granted Feb 17, 2015·85 cites·24 claims
- 0299US8344925B1System and method for adaptive timing control of successive approximation analog-to-digital conversionCADENCE DESIGN SYSTEMS INC·Filed 2011·Granted Jan 1, 2013·69 cites·28 claims
- 0399US7882456B2Optical lithography correction processCADENCE DESIGN SYSTEMS INC·Filed 2005·Granted Feb 1, 2011·150 cites·19 claims
- 0499US7480891B2Method and apparatus of model-based photomask synthesisCADENCE DESIGN SYSTEMS INC·Filed 2005·Granted Jan 20, 2009·248 cites·55 claims
- 0598US8001516B2Characterization and reduction of variation for integrated circuitsCADENCE DESIGN SYSTEMS INC·Filed 2008·Granted Aug 16, 2011·138 cites·61 claims
- 0698US7962867B2Electronic design for integrated circuits based on process related variationsCADENCE DESIGN SYSTEMS INC·Filed 2008·Granted Jun 14, 2011·206 cites·22 claims
- 0798US7712056B2Characterization and verification for integrated circuit designsCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted May 4, 2010·194 cites·36 claims
- 0898US7568174B2Method for checking printability of a lithography targetCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted Jul 28, 2009·185 cites·33 claims
- 0998US7549134B1Method and system for performing crosstalk analysisCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted Jun 16, 2009·196 cites·16 claims
- 1098US7506300B2Apparatus and method for breaking up and merging polygonsCADENCE DESIGN SYSTEMS INC·Filed 2005·Granted Mar 17, 2009·232 cites·27 claims
- 1198US7383521B2Characterization and reduction of variation for integrated circuitsCADENCE DESIGN SYSTEMS INC·Filed 2004·Granted Jun 3, 2008·408 cites·96 claims
- 1298US7367008B2Adjustment of masks for integrated circuit fabricationCADENCE DESIGN SYSTEMS INC·Filed 2002·Granted Apr 29, 2008·286 cites·44 claims
- 1398US7360179B2Use of models in integrated circuit fabricationCADENCE DESIGN SYSTEMS INC·Filed 2005·Granted Apr 15, 2008·266 cites·75 claims
- 1498US7302672B2Method and system for context-specific mask writingCADENCE DESIGN SYSTEMS INC·Filed 2005·Granted Nov 27, 2007·71 cites·24 claims
- 1598US7231628B2Method and system for context-specific mask inspectionCADENCE DESIGN SYSTEMS INC·Filed 2003·Granted Jun 12, 2007·314 cites·19 claims
- 1697US9798840B1Methods, systems, and computer program product for implementing a simulation platform with dynamic device model libraries for electronic designsCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Oct 24, 2017·27 cites·20 claims
- 1797US9223915B1Method, system, and computer program product for checking, verifying, or testing a multi-fabric electronic design spanning across multiple design fabricsCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Dec 29, 2015·39 cites·20 claims
- 1897US8904256B1Method and apparatus for low-pin count testing of integrated circuitsCADENCE DESIGN SYSTEMS INC·Filed 2012·Granted Dec 2, 2014·35 cites·27 claims
- 1997US7926001B2Uniformity for semiconductor patterning operationsCADENCE DESIGN SYSTEMS INC·Filed 2008·Granted Apr 12, 2011·49 cites·18 claims
- 2097US7653892B1System and method for implementing image-based design rulesCADENCE DESIGN SYSTEMS INC·Filed 2005·Granted Jan 26, 2010·48 cites·16 claims
- 2197US7562323B1System, method and computer program product for handling small aggressors in signal integrity analysisCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted Jul 14, 2009·208 cites·19 claims
- 2297US7543262B2Analog layout module generator and methodCADENCE DESIGN SYSTEMS INC·Filed 2005·Granted Jun 2, 2009·138 cites·24 claims
- 2397US7418693B1System and method for analysis and transformation of layouts using situationsCADENCE DESIGN SYSTEMS INC·Filed 2005·Granted Aug 26, 2008·72 cites·10 claims
- 2497US7065731B2Removal of acute angles in a design layoutCADENCE DESIGN SYSTEMS INC·Filed 2003·Granted Jun 20, 2006·201 cites·21 claims
- 2597US6701306B1Methods and apparatus for manipulating polygons in a multidimensional spaceCADENCE DESIGN SYSTEMS INC·Filed 2002·Granted Mar 2, 2004·78 cites·22 claims
- 2697US6631504B2Hierarchical test circuit structure for chips with multiple circuit blocksCADENCE DESIGN SYSTEMS INC·Filed 2001·Granted Oct 7, 2003·122 cites·17 claims
- 2796US11645441B1Machine-learning based clustering for clock tree synthesisCADENCE DESIGN SYSTEMS INC·Filed 2020·Granted May 9, 2023·12 cites·20 claims
- 2896US10963617B1Modifying route topology to fix clock tree violationsCADENCE DESIGN SYSTEMS INC·Filed 2020·Granted Mar 30, 2021·11 cites·20 claims
- 2996US9740814B1Method and system for triple patterning technology (TPT) violation detection and visualizationCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Aug 22, 2017·18 cites·20 claims
- 3096US9285778B1Time to digital converter with successive approximation architectureCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Mar 15, 2016·25 cites·26 claims
- 3196US9135375B1Methods for construction and optimization of a clock tree plan for reduced power consumptionCADENCE DESIGN SYSTEMS INC·Filed 2013·Granted Sep 15, 2015·65 cites·21 claims
- 3296US8788995B1System and method for guiding remedial transformations of a circuit design defined by physical implementation data to reduce needed physical corrections for detected timing violations in the circuit designCADENCE DESIGN SYSTEMS INC·Filed 2013·Granted Jul 22, 2014·55 cites·16 claims
- 3396US8719754B1System and method to generate re-useable layout components from schematic components in an IC design with hierarchical parametersCADENCE DESIGN SYSTEMS INC·Filed 2013·Granted May 6, 2014·35 cites·20 claims
- 3496US8384453B1Frequency adjustment in a control systemCADENCE DESIGN SYSTEMS INC·Filed 2012·Granted Feb 26, 2013·22 cites·21 claims
- 3596US8375348B1Method, system, and program product to implement colored tiles for detail routing for double pattern lithographyCADENCE DESIGN SYSTEMS INC·Filed 2010·Granted Feb 12, 2013·41 cites·24 claims
- 3696US8365113B1Flow methodology for single pass parallel hierarchical timing closure of integrated circuit designsCADENCE DESIGN SYSTEMS INC·Filed 2010·Granted Jan 29, 2013·51 cites·31 claims
- 3796US8001512B1Method and system for implementing context simulationCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted Aug 16, 2011·66 cites·38 claims
- 3896US7882471B1Timing and signal integrity analysis of integrated circuits with semiconductor process variationsCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted Feb 1, 2011·56 cites·23 claims
- 3996US7818707B1Fast pattern matchingCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted Oct 19, 2010·36 cites·25 claims
- 4096US7774735B1Integrated circuit netlist migrationCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted Aug 10, 2010·245 cites·21 claims
- 4196US7487475B1Systems, methods, and apparatus to perform statistical static timing analysisCADENCE DESIGN SYSTEMS INC·Filed 2005·Granted Feb 3, 2009·299 cites·23 claims
- 4296US7418683B1Constraint assistant for circuit designCADENCE DESIGN SYSTEMS INC·Filed 2005·Granted Aug 26, 2008·127 cites·21 claims
- 4396US7393755B2Dummy fill for integrated circuitsCADENCE DESIGN SYSTEMS INC·Filed 2002·Granted Jul 1, 2008·104 cites·79 claims
- 4496US7363099B2Integrated circuit metrologyCADENCE DESIGN SYSTEMS INC·Filed 2002·Granted Apr 22, 2008·71 cites·102 claims
- 4596US7073140B1Method and system for performing crosstalk analysisCADENCE DESIGN SYSTEMS INC·Filed 2003·Granted Jul 4, 2006·198 cites·47 claims
- 4696US6971076B2Method for estimating peak crosstalk noise based on separate crosstalk modelCADENCE DESIGN SYSTEMS INC·Filed 2002·Granted Nov 29, 2005·192 cites·15 claims
- 4796US6711727B1Method and arrangement for layout and manufacture of gridless nonManhattan semiconductor integrated circuitsCADENCE DESIGN SYSTEMS INC·Filed 2001·Granted Mar 23, 2004·91 cites·20 claims
- 4896US6594799B1Method and system for facilitating electronic circuit and chip design using remotely located resourcesCADENCE DESIGN SYSTEMS INC·Filed 2000·Granted Jul 15, 2003·224 cites·64 claims
- 4996US6526555B1Method for layout and manufacture of gridless non manhattan semiconductor integrated circuits using compactionCADENCE DESIGN SYSTEMS INC·Filed 2001·Granted Feb 25, 2003·104 cites·20 claims
- 5096US6516455B1Partitioning placement method using diagonal cutlinesCADENCE DESIGN SYSTEMS INC·Filed 2001·Granted Feb 4, 2003·127 cites·17 claims
Showing the top 50 of 2,048 patent records by PatentIndex Score.
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