Assignee
CHACHAD ABHIJEET ASHOK
US·8 granted patents·2 pending applications·9 citations·filing 2011–2012
Top patents by PatentIndex Score
10 records- 0188US9009408B2Non-blocking, pipelined write allocates with allocate data merging in a multi-level cache systemCHACHAD ABHIJEET ASHOK·Filed 2011·Granted Apr 14, 2015·5 cites·4 claims
- 0287US8904115B2Cache with multiple access pipelinesCHACHAD ABHIJEET ASHOK·Filed 2011·Granted Dec 2, 2014·4 cites·2 claims
- 0361US8683137B2Cache pre-allocation of ways for pipelined allocate requestsCHACHAD ABHIJEET ASHOK·Filed 2011·Granted Mar 25, 2014·0 cites·4 claims
- 0461US8661199B2Efficient level two memory banking to improve performance for multiple source traffic and enable deeper pipelining of accesses by reducing bank stallsCHACHAD ABHIJEET ASHOK·Filed 2011·Granted Feb 25, 2014·0 cites·2 claims
- 0560US8732398B2Enhanced pipelining and multi-buffer architecture for level two cache controller to minimize hazard stalls and optimize performanceCHACHAD ABHIJEET ASHOK·Filed 2011·Granted May 20, 2014·0 cites·16 claims
- 0658US8856446B2Hazard prevention for data conflicts between level one data cache line allocates and snoop writesCHACHAD ABHIJEET ASHOK·Filed 2011·Granted Oct 7, 2014·0 cites·3 claims
- 0757US8607000B2Efficient cache allocation by optimizing size and order of allocate commands based on bytes required by CPUCHACHAD ABHIJEET ASHOK·Filed 2011·Granted Dec 10, 2013·0 cites·13 claims
- 0857US2012290755A1Lookahead Priority Collection to Support Priority ElevationCHACHAD ABHIJEET ASHOK·Filed 2011·Application pending·0 cites
- 0943US8488405B2Process variability tolerant programmable memory controller for a pipelined memory systemCHACHAD ABHIJEET ASHOK·Filed 2011·Granted Jul 16, 2013·0 cites·8 claims
- 1043US2013326155A1System and method of optimized user coherence for a cache block with sparse dirty linesCHACHAD ABHIJEET ASHOK·Filed 2012·Application pending·0 cites
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