Assignee
CHAN YUEN H
US·4 granted patents·2 pending applications·8 citations·filing 2008–2011
Top patents by PatentIndex Score
6 records- 0161US8233331B2Single clock dynamic compare circuitCHAN YUEN H·Filed 2010·Granted Jul 31, 2012·2 cites·16 claims
- 0258US8587990B2Global bit line restore by most significant bit of an address lineCHAN YUEN H·Filed 2011·Granted Nov 19, 2013·2 cites·15 claims
- 0352US8237481B2Low power programmable clock delay generator with integrated decode functionCHAN YUEN H·Filed 2008·Granted Aug 7, 2012·2 cites·5 claims
- 0451US8339893B2Dual beta ratio SRAMCHAN YUEN H·Filed 2009·Granted Dec 25, 2012·2 cites·4 claims
- 0532US2011317478A1Method and Circuit Arrangement for Performing a Write Through Operation, and SRAM Array With Write Through CapabilityCHAN YUEN H·Filed 2011·Application pending·0 cites
- 0631US2011310680A1Interleave Memory Array ArrangementCHAN YUEN H·Filed 2010·Application pending·0 cites
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