Assignee
CHEN YIRAN
US·20 granted patents·144 citations·filing 2008–2012
Top patents by PatentIndex Score
20 records- 0194US8203899B2Memory cell with proportional current self-reference sensingCHEN YIRAN·Filed 2010·Granted Jun 19, 2012·20 cites·20 claims
- 0290US8296620B2Data devices including multiple error correction codes and methods of utilizingCHEN YIRAN·Filed 2008·Granted Oct 23, 2012·24 cites·23 claims
- 0390US8213215B2Resistive sense memory calibration for self-reference read methodCHEN YIRAN·Filed 2011·Granted Jul 3, 2012·12 cites·20 claims
- 0487US8289746B2MRAM diode array and access methodCHEN YIRAN·Filed 2010·Granted Oct 16, 2012·9 cites·18 claims
- 0587US8116123B2Spin-transfer torque memory non-destructive self-reference read methodCHEN YIRAN·Filed 2008·Granted Feb 14, 2012·15 cites·20 claims
- 0685US9128821B2Data updating in non-volatile memoryCHEN YIRAN·Filed 2009·Granted Sep 8, 2015·12 cites·5 claims
- 0785US8514605B2MRAM diode array and access methodCHEN YIRAN·Filed 2012·Granted Aug 20, 2013·7 cites·20 claims
- 0879US8416614B2Spin-transfer torque memory non-destructive self-reference read methodCHEN YIRAN·Filed 2012·Granted Apr 9, 2013·5 cites·18 claims
- 0979US8081504B2Computer memory device with status registerCHEN YIRAN·Filed 2008·Granted Dec 20, 2011·11 cites·20 claims
- 1078US8199563B2Transmission gate-based spin-transfer torque memory unitCHEN YIRAN·Filed 2011·Granted Jun 12, 2012·7 cites·20 claims
- 1175US8966181B2Memory hierarchy with non-volatile filter and victim cachesCHEN YIRAN·Filed 2008·Granted Feb 24, 2015·7 cites·19 claims
- 1274US8416615B2Transmission gate-based spin-transfer torque memory unitCHEN YIRAN·Filed 2012·Granted Apr 9, 2013·5 cites·20 claims
- 1365US8154914B2Predictive thermal preconditioning and timing control for non-volatile memory cellsCHEN YIRAN·Filed 2011·Granted Apr 10, 2012·2 cites·20 claims
- 1465US8139397B2Spatial correlation of reference cells in resistive memory arrayCHEN YIRAN·Filed 2010·Granted Mar 20, 2012·2 cites·20 claims
- 1558US8526215B2Spatial correlation of reference cells in resistive memory arrayCHEN YIRAN·Filed 2012·Granted Sep 3, 2013·1 cites·20 claims
- 1656US8194437B2Computer memory device with multiple interfacesCHEN YIRAN·Filed 2009·Granted Jun 5, 2012·3 cites·17 claims
- 1753US8203862B2Voltage reference generation with selectable dummy regionsCHEN YIRAN·Filed 2009·Granted Jun 19, 2012·2 cites·18 claims
- 1845US8553454B2Predictive thermal preconditioning and timing control for non-volatile memory cellsCHEN YIRAN·Filed 2012·Granted Oct 8, 2013·0 cites·20 claims
- 1941US8934281B2Bit set modes for a resistive sense memory cell arrayCHEN YIRAN·Filed 2011·Granted Jan 13, 2015·0 cites·20 claims
- 2038US8942035B2Non-sequential encoding scheme for multi-level cell (MLC) memory cellsCHEN YIRAN·Filed 2011·Granted Jan 27, 2015·0 cites·20 claims
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