Assignee
DEVTA-PRASANNA NARENDRA B
US·2 granted patents·7 citations·filing 2009–2010
Technology mixG01R2
Top patents by PatentIndex Score
2 records- 0179US8412994B2Design-for-test technique to reduce test volume including a clock gate controllerDEVTA-PRASANNA NARENDRA B·Filed 2010·Granted Apr 2, 2013·6 cites·20 claims
- 0246US8515695B2Method and an apparatus for evaluating small delay defect coverage of a test pattern set on an ICDEVTA-PRASANNA NARENDRA B·Filed 2009·Granted Aug 20, 2013·1 cites·20 claims
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