Assignee
DRERUP BERNARD CHARLES
US·2 granted patents·4 citations·filing 2007–2008
Technology mixG06F2
Top patents by PatentIndex Score
2 records- 0165US8266386B2Structure for maintaining memory data integrity in a processor integrated circuit using cache coherency protocolsDRERUP BERNARD CHARLES·Filed 2008·Granted Sep 11, 2012·4 cites·30 claims
- 0244US8108618B2Method and apparatus for maintaining memory data integrity in an information handling system using cache coherency protocolsDRERUP BERNARD CHARLES·Filed 2007·Granted Jan 31, 2012·0 cites·24 claims
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