Assignee
EXPONENTIAL TECHN INC
US·34 granted patents·3,993 citations·filing 1994–1997
Top patents by PatentIndex Score
34 records- 0198US5598546ADual-architecture super-scalar pipelineEXPONENTIAL TECHN INC·Filed 1994·Granted Jan 28, 1997·390 cites·21 claims
- 0297US5477082ABi-planar multi-chip moduleEXPONENTIAL TECHN INC·Filed 1994·Granted Dec 19, 1995·327 cites·13 claims
- 0394US5781750ADual-instruction-set architecture CPU with hidden software emulation modeEXPONENTIAL TECHN INC·Filed 1994·Granted Jul 14, 1998·209 cites·20 claims
- 0494US5481684AEmulating operating system calls in an alternate instruction set using a modified code segment descriptorEXPONENTIAL TECHN INC·Filed 1994·Granted Jan 2, 1996·231 cites·6 claims
- 0592US5481693AShared register architecture for a dual-instruction-set CPUEXPONENTIAL TECHN INC·Filed 1994·Granted Jan 2, 1996·153 cites·7 claims
- 0691US5781457AMerge/mask, rotate/shift, and boolean operations from two instruction sets executed in a vectored mux on a dual-ALUEXPONENTIAL TECHN INC·Filed 1996·Granted Jul 14, 1998·189 cites·16 claims
- 0791US5757690AEmbedded ROM with RAM valid bits for fetching ROM-code updates from external memoryEXPONENTIAL TECHN INC·Filed 1997·Granted May 26, 1998·125 cites·20 claims
- 0891US5745913AMulti-processor DRAM controller that prioritizes row-miss requests to stale banksEXPONENTIAL TECHN INC·Filed 1996·Granted Apr 28, 1998·207 cites·19 claims
- 0991US5542059ADual instruction set processor having a pipeline with a pipestage functional unit that is relocatable in time and sequence orderEXPONENTIAL TECHN INC·Filed 1994·Granted Jul 30, 1996·159 cites·16 claims
- 1091US5477489AHigh-stability CMOS multi-port register file memory cell with column isolation and current-mirror row line driverEXPONENTIAL TECHN INC·Filed 1995·Granted Dec 19, 1995·93 cites·21 claims
- 1190US5732209ASelf-testing multi-processor die with internal compare pointsEXPONENTIAL TECHN INC·Filed 1996·Granted Mar 24, 1998·306 cites·19 claims
- 1286US5551001AMaster-slave cache system for instruction and data cache memoriesEXPONENTIAL TECHN INC·Filed 1994·Granted Aug 27, 1996·132 cites·16 claims
- 1385US5440710AEmulation of segment bounds checking using paging with sub-page validityEXPONENTIAL TECHN INC·Filed 1994·Granted Aug 8, 1995·97 cites·25 claims
- 1483US5453949ABiCMOS Static RAM with active-low word lineEXPONENTIAL TECHN INC·Filed 1994·Granted Sep 26, 1995·52 cites·15 claims
- 1582US5685009AShared floating-point registers and register port-pairing in a dual-architecture CPUEXPONENTIAL TECHN INC·Filed 1995·Granted Nov 4, 1997·113 cites·19 claims
- 1682US5664159AMethod for emulating multiple debug breakpoints by page partitioning using a single breakpoint registerEXPONENTIAL TECHN INC·Filed 1995·Granted Sep 2, 1997·106 cites·18 claims
- 1782US5608886ABlock-based branch prediction using a target finder array storing target sub-addressesEXPONENTIAL TECHN INC·Filed 1994·Granted Mar 4, 1997·100 cites·21 claims
- 1881US5692152AMaster-slave cache system with de-coupled data and tag pipelines and loop-backEXPONENTIAL TECHN INC·Filed 1996·Granted Nov 25, 1997·106 cites·19 claims
- 1980US5884057ATemporal re-alignment of a floating point pipeline to an integer pipeline for emulation of a load-operate architecture on a load/store processorEXPONENTIAL TECHN INC·Filed 1995·Granted Mar 16, 1999·103 cites·14 claims
- 2078US5687336AStack push/pop tracking and pairing in a pipelined processorEXPONENTIAL TECHN INC·Filed 1996·Granted Nov 11, 1997·84 cites·19 claims
- 2177US5644752ACombined store queue for a master-slave cache systemEXPONENTIAL TECHN INC·Filed 1994·Granted Jul 1, 1997·80 cites·19 claims
- 2277US5634118ASplitting a floating-point stack-exchange instruction for merging into surrounding instructions by operand translationEXPONENTIAL TECHN INC·Filed 1995·Granted May 27, 1997·82 cites·20 claims
- 2376US5652872ATranslator having segment bounds encoding for storage in a TLBEXPONENTIAL TECHN INC·Filed 1995·Granted Jul 29, 1997·81 cites·20 claims
- 2476US5542109AAddress tracking and branch resolution in a processor with multiple execution pipelines and instruction stream discontinuitiesEXPONENTIAL TECHN INC·Filed 1994·Granted Jul 30, 1996·73 cites·10 claims
- 2575US5784590ASlave cache having sub-line valid bits updated by a master cacheEXPONENTIAL TECHN INC·Filed 1996·Granted Jul 21, 1998·78 cites·21 claims
- 2670US5442577ASign-extension of immediate constants in an aluEXPONENTIAL TECHN INC·Filed 1994·Granted Aug 15, 1995·46 cites·13 claims
- 2769US5751614ASign-extension merge/mask, rotate/shift, and boolean operations executed in a vectored mux on an ALUEXPONENTIAL TECHN INC·Filed 1996·Granted May 12, 1998·56 cites·18 claims
- 2869US5598553AProgram watchpoint checking using paging with sub-page validityEXPONENTIAL TECHN INC·Filed 1995·Granted Jan 28, 1997·49 cites·25 claims
- 2962US5633819AInexact leading-one/leading-zero prediction integrated with a floating-point adderEXPONENTIAL TECHN INC·Filed 1995·Granted May 27, 1997·44 cites·19 claims
- 3060US5809272AEarly instruction-length pre-decode of variable-length instructions in a superscalar processorEXPONENTIAL TECHN INC·Filed 1995·Granted Sep 15, 1998·39 cites·19 claims
- 3154US5548545AFloating point exception prediction for compound operations and variable precision using an intermediate exponent busEXPONENTIAL TECHN INC·Filed 1995·Granted Aug 20, 1996·31 cites·17 claims
- 3253US5511017AReduced-modulus address generation using sign-extension and correctionEXPONENTIAL TECHN INC·Filed 1994·Granted Apr 23, 1996·25 cites·22 claims
- 3346US5574677AAdaptive non-restoring integer divide apparatus with integrated overflow detectEXPONENTIAL TECHN INC·Filed 1994·Granted Nov 12, 1996·16 cites·17 claims
- 3441US5497341ASign-extension of immediate constants in an ALU using an adder in an integer logic unitEXPONENTIAL TECHN INC·Filed 1995·Granted Mar 5, 1996·11 cites·20 claims
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