Assignee
FLEISCHER BRUCE M
US·13 granted patents·31 citations·filing 2008–2012
Top patents by PatentIndex Score
13 records- 0196US8188761B2Soft error detection for latchesFLEISCHER BRUCE M·Filed 2011·Granted May 29, 2012·18 cites·16 claims
- 0274US9632777B2Gather/scatter of multiple data elements with packed loading/storing into/from a register file entryFLEISCHER BRUCE M·Filed 2012·Granted Apr 25, 2017·3 cites·18 claims
- 0373US9569211B2Predication in a vector processorFLEISCHER BRUCE M·Filed 2012·Granted Feb 14, 2017·4 cites·13 claims
- 0470US9575756B2Predication in a vector processorFLEISCHER BRUCE M·Filed 2012·Granted Feb 21, 2017·2 cites·13 claims
- 0564US9582466B2Vector register fileFLEISCHER BRUCE M·Filed 2012·Granted Feb 28, 2017·1 cites·17 claims
- 0662US8560924B2Register file soft error recoveryFLEISCHER BRUCE M·Filed 2010·Granted Oct 15, 2013·1 cites·18 claims
- 0761US8656332B2Automated critical area allocation in a physical synthesized hierarchical designFLEISCHER BRUCE M·Filed 2009·Granted Feb 18, 2014·2 cites·20 claims
- 0852US9575755B2Vector processing in an active memory deviceFLEISCHER BRUCE M·Filed 2012·Granted Feb 21, 2017·0 cites·19 claims
- 0952US9535694B2Vector processing in an active memory deviceFLEISCHER BRUCE M·Filed 2012·Granted Jan 3, 2017·0 cites·18 claims
- 1051US9632778B2Gather/scatter of multiple data elements with packed loading/storing into /from a register file entryFLEISCHER BRUCE M·Filed 2012·Granted Apr 25, 2017·0 cites·18 claims
- 1151US9594724B2Vector register fileFLEISCHER BRUCE M·Filed 2012·Granted Mar 14, 2017·0 cites·17 claims
- 1249US8069195B2Method and system for a wiring-efficient permute unitFLEISCHER BRUCE M·Filed 2008·Granted Nov 29, 2011·0 cites·13 claims
- 1345US9003160B2Active buffered memoryFLEISCHER BRUCE M·Filed 2012·Granted Apr 7, 2015·0 cites·28 claims
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