Assignee
GOPALAKRISHNAN PRAKASH
US·5 granted patents·64 citations·filing 2008–2012
Technology mixG06F5
Top patents by PatentIndex Score
5 records- 0192US8261228B1Technique for modeling parasitics from layout during circuit design and for parasitic aware circuit design using modes of varying accuracyGOPALAKRISHNAN PRAKASH·Filed 2008·Granted Sep 4, 2012·42 cites·14 claims
- 0285US8584072B1Technique for modeling parasitics from layout during circuit design and for parasitic aware circuit design using modes of varying accuracyGOPALAKRISHNAN PRAKASH·Filed 2012·Granted Nov 12, 2013·9 cites·17 claims
- 0383US8694933B2Methods, systems, and articles of manufacture for implementing electronic circuit designs with simulation awarenessGOPALAKRISHNAN PRAKASH·Filed 2010·Granted Apr 8, 2014·5 cites·54 claims
- 0481US8612921B1Technique for modeling parasitics from layout during circuit design and for parasitic aware circuit design using modes of varying accuracyGOPALAKRISHNAN PRAKASH·Filed 2012·Granted Dec 17, 2013·6 cites·8 claims
- 0560US8527928B1Optimizing circuit layouts by configuring rooms for placing devicesGOPALAKRISHNAN PRAKASH·Filed 2009·Granted Sep 3, 2013·2 cites·20 claims
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