Assignee
INNOVATIVE SILICON ISI SA
CH·19 granted patents·3,207 citations·filing 2005–2008
Top patents by PatentIndex Score
19 records- 0199US7733693B2Semiconductor memory device and method of operating sameINNOVATIVE SILICON ISI SA·Filed 2008·Granted Jun 8, 2010·222 cites·20 claims
- 0299US7541616B2Semiconductor deviceINNOVATIVE SILICON ISI SA·Filed 2007·Granted Jun 2, 2009·257 cites·20 claims
- 0399US7542345B2Multi-bit memory cell having electrically floating body transistor, and method of programming and reading sameINNOVATIVE SILICON ISI SA·Filed 2007·Granted Jun 2, 2009·335 cites·25 claims
- 0499US7514748B2Semiconductor deviceINNOVATIVE SILICON ISI SA·Filed 2005·Granted Apr 7, 2009·261 cites·26 claims
- 0599US7492632B2Memory array having a programmable word length, and method of operating sameINNOVATIVE SILICON ISI SA·Filed 2007·Granted Feb 17, 2009·397 cites·31 claims
- 0699US7486563B2Sense amplifier circuitry and architecture to write data into and/or read from memory cellsINNOVATIVE SILICON ISI SA·Filed 2007·Granted Feb 3, 2009·274 cites·25 claims
- 0799US7476939B2Memory cell having an electrically floating body transistor and programming technique thereforINNOVATIVE SILICON ISI SA·Filed 2005·Granted Jan 13, 2009·295 cites·26 claims
- 0899US7477540B2Bipolar reading technique for a memory cell having an electrically floating body transistorINNOVATIVE SILICON ISI SA·Filed 2007·Granted Jan 13, 2009·388 cites·33 claims
- 0998US7606066B2Memory cell and memory cell array having an electrically floating body transistor, and methods of operating sameINNOVATIVE SILICON ISI SA·Filed 2006·Granted Oct 20, 2009·90 cites·42 claims
- 1098US7542340B2Integrated circuit including memory array having a segmented bit line architecture and method of controlling and/or operating sameINNOVATIVE SILICON ISI SA·Filed 2007·Granted Jun 2, 2009·104 cites·28 claims
- 1198US7499352B2Integrated circuit having memory array including row redundancy, and method of programming, controlling and/or operating sameINNOVATIVE SILICON ISI SA·Filed 2007·Granted Mar 3, 2009·262 cites·22 claims
- 1298US7499358B2Method and circuitry to generate a reference current for reading a memory cell, and device implementing sameINNOVATIVE SILICON ISI SA·Filed 2008·Granted Mar 3, 2009·260 cites·20 claims
- 1395US7683430B2Electrically floating body memory cell and array, and method of operating or controlling sameINNOVATIVE SILICON ISI SA·Filed 2006·Granted Mar 23, 2010·34 cites·35 claims
- 1488US7732816B2Semiconductor deviceINNOVATIVE SILICON ISI SA·Filed 2007·Granted Jun 8, 2010·7 cites·20 claims
- 1573US7619944B2Method and apparatus for variable memory cell refreshINNOVATIVE SILICON ISI SA·Filed 2007·Granted Nov 17, 2009·8 cites·28 claims
- 1668US7606098B2Semiconductor memory array architecture with grouped memory cells, and method of controlling sameINNOVATIVE SILICON ISI SA·Filed 2007·Granted Oct 20, 2009·6 cites·28 claims
- 1764US7736959B2Integrated circuit device, and method of fabricating sameINNOVATIVE SILICON ISI SA·Filed 2008·Granted Jun 15, 2010·2 cites·17 claims
- 1847US7602645B2Method and apparatus for varying the programming duration and/or voltage of an electrically floating body transistor, and memory cell array implementing sameINNOVATIVE SILICON ISI SA·Filed 2008·Granted Oct 13, 2009·2 cites·21 claims
- 1938US7787319B2Sense amplifier circuitry for integrated circuit having memory cell array, and method of operating sameINNOVATIVE SILICON ISI SA·Filed 2008·Granted Aug 31, 2010·3 cites·15 claims
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