Assignee

JASPER DESIGN AUTOMATION

US·4 granted patents·150 citations·filing 2003–2012

Technology mixG06F4

Top patents by PatentIndex Score

4 records

0192US8381148B1Formal verification of deadlock propertyJASPER DESIGN AUTOMATION·Filed 2012·Granted Feb 19, 2013·35 cites·35 claims
0290US7159198B1System and method for identifying design efficiency and effectiveness parameters for verifying properties of a circuit modelJASPER DESIGN AUTOMATION·Filed 2003·Granted Jan 2, 2007·63 cites·66 claims
0387US7437694B1System and method for determining and identifying signals that are relevantly determined by a selected signal in a circuit designJASPER DESIGN AUTOMATION·Filed 2005·Granted Oct 14, 2008·21 cites·19 claims
0487US7412674B1System and method for measuring progress for formal verification of a design using analysis regionJASPER DESIGN AUTOMATION·Filed 2005·Granted Aug 12, 2008·31 cites·22 claims

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