Assignee
KELLER IGOR
US·5 granted patents·124 citations·filing 2008–2012
Technology mixG06F5
Top patents by PatentIndex Score
5 records- 0194US8595669B1Flexible noise and delay modeling of circuit stages for static timing analysis of integrated circuit designsKELLER IGOR·Filed 2008·Granted Nov 26, 2013·39 cites·26 claims
- 0292US8601420B1Equivalent waveform model for static timing analysis of integrated circuit designsKELLER IGOR·Filed 2010·Granted Dec 3, 2013·27 cites·30 claims
- 0391US8543954B1Concurrent noise and delay modeling of circuit stages for static timing analysis of integrated circuit designsKELLER IGOR·Filed 2008·Granted Sep 24, 2013·28 cites·28 claims
- 0489US8302046B1Compact modeling of circuit stages for static timing analysis of integrated circuit designsKELLER IGOR·Filed 2008·Granted Oct 30, 2012·20 cites·18 claims
- 0588US8615725B1Methods for compact modeling of circuit stages for static timing analysis of integrated circuit designsKELLER IGOR·Filed 2012·Granted Dec 24, 2013·10 cites·23 claims
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