Assignee
LEE JIN-YUAN
TW·18 granted patents·4 pending applications·120 citations·filing 2003–2011
Top patents by PatentIndex Score
22 records- 0196US8072070B2Low fabrication cost, fine pitch and high reliability solder bumpLEE JIN-YUAN·Filed 2009·Granted Dec 6, 2011·32 cites·23 claims
- 0291US8461679B2Method for fabricating circuit componentLEE JIN-YUAN·Filed 2011·Granted Jun 11, 2013·9 cites·22 claims
- 0388US9142527B2Method of wire bonding over active area of a semiconductor circuitLEE JIN-YUAN·Filed 2007·Granted Sep 22, 2015·11 cites·18 claims
- 0485US8138079B2Method of wire bonding over active area of a semiconductor circuitLEE JIN-YUAN·Filed 2007·Granted Mar 20, 2012·8 cites·38 claims
- 0583US9369175B2Low fabrication cost, high performance, high reliability chip scale packageLEE JIN-YUAN·Filed 2007·Granted Jun 14, 2016·9 cites·24 claims
- 0682US8124446B2Structure of high performance combo chip and processing methodLEE JIN-YUAN·Filed 2007·Granted Feb 28, 2012·6 cites·23 claims
- 0781US9018774B2Chip packageLEE JIN-YUAN·Filed 2008·Granted Apr 28, 2015·6 cites·63 claims
- 0881US8193636B2Chip assembly with interconnection by metal bumpLEE JIN-YUAN·Filed 2008·Granted Jun 5, 2012·10 cites·17 claims
- 0979US9153555B2Method of wire bonding over active area of a semiconductor circuitLEE JIN-YUAN·Filed 2007·Granted Oct 6, 2015·5 cites·24 claims
- 1078US8481418B2Low fabrication cost, high performance, high reliability chip scale packageLEE JIN-YUAN·Filed 2007·Granted Jul 9, 2013·6 cites·42 claims
- 1176US8426982B2Structure and manufacturing method of chip scale packageLEE JIN-YUAN·Filed 2009·Granted Apr 23, 2013·4 cites·29 claims
- 1274US8334588B2Circuit component with conductive layer structureLEE JIN-YUAN·Filed 2011·Granted Dec 18, 2012·3 cites·25 claims
- 1372US8178967B2Low fabrication cost, high performance, high reliability chip scale packageLEE JIN-YUAN·Filed 2007·Granted May 15, 2012·3 cites·23 claims
- 1467US8890336B2Cylindrical bonding structure and method of manufactureLEE JIN-YUAN·Filed 2008·Granted Nov 18, 2014·2 cites·20 claims
- 1559US8535976B2Method for fabricating chip package with die and substrateLEE JIN-YUAN·Filed 2003·Granted Sep 17, 2013·6 cites·43 claims
- 1655US8748227B2Method of fabricating chip packageLEE JIN-YUAN·Filed 2008·Granted Jun 10, 2014·0 cites·55 claims
- 1753US8742580B2Method of wire bonding over active area of a semiconductor circuitLEE JIN-YUAN·Filed 2007·Granted Jun 3, 2014·0 cites·29 claims
- 1853US8546947B2Chip structure and process for forming the sameLEE JIN-YUAN·Filed 2011·Granted Oct 1, 2013·0 cites·30 claims
- 1950US2008169024A1Photovoltaic deviceLEE JIN-YUAN·Filed 2007·Application pending·0 cites
- 2047US2007166901A1Method for fabricating soi deviceLEE JIN-YUAN·Filed 2007·Application pending·0 cites
- 2144US2007090456A1Soi device and method for fabricating the sameLEE JIN-YUAN·Filed 2005·Application pending·0 cites
- 2239US2007210380A1Body connection structure for soi mos transistorLEE JIN-YUAN·Filed 2006·Application pending·0 cites
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Counts cover granted patents and pending applications in the PatentIndex corpus. How scoring works →