Assignee
LESEA AUSTIN H
US·8 granted patents·136 citations·filing 2008–2011
Top patents by PatentIndex Score
8 records- 0197US8516339B1Method of and circuit for correcting adjacent bit errors in a memoryLESEA AUSTIN H·Filed 2011·Granted Aug 20, 2013·47 cites·19 claims
- 0294US8522052B1Method and integrated circuit for secure encryption and decryptionLESEA AUSTIN H·Filed 2010·Granted Aug 27, 2013·28 cites·12 claims
- 0387US9213835B2Method and integrated circuit for secure encryption and decryptionLESEA AUSTIN H·Filed 2010·Granted Dec 15, 2015·11 cites·13 claims
- 0487US8117497B1Method and apparatus for error upset detection and correctionLESEA AUSTIN H·Filed 2008·Granted Feb 14, 2012·17 cites·18 claims
- 0583US8146028B1Duplicate design flow for mitigation of soft errors in IC operationLESEA AUSTIN H·Filed 2008·Granted Mar 27, 2012·12 cites·16 claims
- 0681US8397191B1Determining failure rate from circuit design layoutsLESEA AUSTIN H·Filed 2011·Granted Mar 12, 2013·6 cites·20 claims
- 0780US8773929B1Single-event-upset resistant memory cell with triple wellLESEA AUSTIN H·Filed 2008·Granted Jul 8, 2014·12 cites·19 claims
- 0866US8155907B1Methods of enabling functions of a design to be implemented in an integrated circuit device and a computer program productLESEA AUSTIN H·Filed 2009·Granted Apr 10, 2012·3 cites·20 claims
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