Assignee

MORIMOTO MASAO

JP·1 granted patent·12 citations·filing 2012–2012

Technology mixG06F1 G11C1 H01L1 H10B1 H10D1 H10W1

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0190US8957459B2Semiconductor device including memory cell with transistors disposed in different active regionsMORIMOTO MASAO·Filed 2012·Granted Feb 17, 2015·12 cites·5 claims

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