Assignee
MUFF ADAM J
US·13 granted patents·68 citations·filing 2007–2012
Top patents by PatentIndex Score
13 records- 0191US8751830B2Memory address translation-based data encryption/compressionMUFF ADAM J·Filed 2012·Granted Jun 10, 2014·16 cites·22 claims
- 0284US9032191B2Virtualization support for branch prediction logic enable / disable at hypervisor and guest operating system levelsMUFF ADAM J·Filed 2012·Granted May 12, 2015·8 cites·25 claims
- 0384US8954755B2Memory address translation-based data encryption with integrated encryption engineMUFF ADAM J·Filed 2012·Granted Feb 10, 2015·7 cites·25 claims
- 0481US8935694B2System and method for selectively saving and restoring state of branch prediction logic through separate hypervisor-mode and guest-mode and/or user-mode instructionsMUFF ADAM J·Filed 2012·Granted Jan 13, 2015·6 cites·23 claims
- 0580US9251116B2Direct interthread communication dataport pack/unpack and load/saveMUFF ADAM J·Filed 2011·Granted Feb 2, 2016·6 cites·23 claims
- 0675US9465613B2Instruction predication using unused datapath facilitiesMUFF ADAM J·Filed 2011·Granted Oct 11, 2016·3 cites·20 claims
- 0774US8326904B2Trigonometric summation vector execution unitMUFF ADAM J·Filed 2009·Granted Dec 4, 2012·6 cites·10 claims
- 0873US8892851B2Changing opcode of subsequent instruction when same destination address is not used as source address by intervening instructionsMUFF ADAM J·Filed 2011·Granted Nov 18, 2014·3 cites·22 claims
- 0972US9632779B2Instruction predication using instruction filteringMUFF ADAM J·Filed 2011·Granted Apr 25, 2017·3 cites·21 claims
- 1072US8984260B2Predecode logic autovectorizing a group of scalar instructions including result summing add instruction to a vector instruction for execution in vector unit with dot product adderMUFF ADAM J·Filed 2011·Granted Mar 17, 2015·3 cites·21 claims
- 1169US8239439B2Method and apparatus implementing a minimal area consumption multiple addend floating point summation function in a vector microprocessorMUFF ADAM J·Filed 2007·Granted Aug 7, 2012·4 cites·22 claims
- 1267US8102884B2Direct inter-thread communication buffer that supports software controlled arbitrary vector operand selection in a densely threaded network on a chipMUFF ADAM J·Filed 2008·Granted Jan 24, 2012·3 cites·20 claims
- 1343US9632786B2Instruction set architecture with extended register addressing using one or more primary opcode bitsMUFF ADAM J·Filed 2011·Granted Apr 25, 2017·0 cites·24 claims
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