Assignee
RAJAN SURESH NATARAJAN
US·31 granted patents·2 pending applications·1,506 citations·filing 2006–2012
Top patents by PatentIndex Score
33 records- 0199US8667312B2Performing power management operationsRAJAN SURESH NATARAJAN·Filed 2012·Granted Mar 4, 2014·76 cites·20 claims
- 0299US8407412B2Power management of memory circuits by virtual memory simulationRAJAN SURESH NATARAJAN·Filed 2012·Granted Mar 26, 2013·66 cites·20 claims
- 0399US8181048B2Performing power management operationsRAJAN SURESH NATARAJAN·Filed 2010·Granted May 15, 2012·67 cites·34 claims
- 0499US8122207B2Apparatus and method for power management of memory circuits by a system or component thereofRAJAN SURESH NATARAJAN·Filed 2010·Granted Feb 21, 2012·71 cites·22 claims
- 0598US8745321B2Simulating a memory standardRAJAN SURESH NATARAJAN·Filed 2012·Granted Jun 3, 2014·68 cites·13 claims
- 0698US8671244B2Simulating a memory standardRAJAN SURESH NATARAJAN·Filed 2011·Granted Mar 11, 2014·66 cites·13 claims
- 0798US8601204B2Simulating a refresh operation latencyRAJAN SURESH NATARAJAN·Filed 2011·Granted Dec 3, 2013·70 cites·19 claims
- 0898US8595419B2Memory apparatus operable to perform a power-saving operationRAJAN SURESH NATARAJAN·Filed 2011·Granted Nov 26, 2013·68 cites·31 claims
- 0998US8566556B2Memory module with memory stack and interface with enhanced capabilitiesRAJAN SURESH NATARAJAN·Filed 2011·Granted Oct 22, 2013·68 cites·20 claims
- 1098US8446781B1Multi-rank partial width memory modulesRAJAN SURESH NATARAJAN·Filed 2012·Granted May 21, 2013·81 cites·20 claims
- 1198US8340953B2Memory circuit simulation with power saving capabilitiesRAJAN SURESH NATARAJAN·Filed 2006·Granted Dec 25, 2012·75 cites·32 claims
- 1298US8280714B2Memory circuit simulation system and method with refresh capabilitiesRAJAN SURESH NATARAJAN·Filed 2006·Granted Oct 2, 2012·66 cites·33 claims
- 1398US8244971B2Memory circuit system and methodRAJAN SURESH NATARAJAN·Filed 2007·Granted Aug 14, 2012·86 cites·33 claims
- 1498US8154935B2Delaying a signal communicated from a system to at least one of a plurality of memory circuitsRAJAN SURESH NATARAJAN·Filed 2010·Granted Apr 10, 2012·69 cites·37 claims
- 1598US8130560B1Multi-rank partial width memory modulesRAJAN SURESH NATARAJAN·Filed 2007·Granted Mar 6, 2012·131 cites·30 claims
- 1698US8112266B2Apparatus for simulating an aspect of a memory circuitRAJAN SURESH NATARAJAN·Filed 2007·Granted Feb 7, 2012·70 cites·19 claims
- 1798US8090897B2System and method for simulating an aspect of a memory circuitRAJAN SURESH NATARAJAN·Filed 2007·Granted Jan 3, 2012·73 cites·20 claims
- 1897US8209479B2Memory circuit system and methodRAJAN SURESH NATARAJAN·Filed 2007·Granted Jun 26, 2012·85 cites·32 claims
- 1996US8335894B1Configurable memory system with interface circuitRAJAN SURESH NATARAJAN·Filed 2009·Granted Dec 18, 2012·52 cites·24 claims
- 2095US8213205B2Memory system including multiple memory stacksRAJAN SURESH NATARAJAN·Filed 2009·Granted Jul 3, 2012·23 cites·46 claims
- 2194US8868829B2Memory circuit system and methodRAJAN SURESH NATARAJAN·Filed 2012·Granted Oct 21, 2014·17 cites·24 claims
- 2293US8811065B2Performing error detection on DRAMsRAJAN SURESH NATARAJAN·Filed 2012·Granted Aug 19, 2014·10 cites·20 claims
- 2392US8797779B2Memory module with memory stack and interface with enhanced capabilitesRAJAN SURESH NATARAJAN·Filed 2012·Granted Aug 5, 2014·12 cites·20 claims
- 2490US8582339B2System including memory stacksRAJAN SURESH NATARAJAN·Filed 2012·Granted Nov 12, 2013·7 cites·28 claims
- 2588US8819356B2Configurable multirank memory system with interface circuitRAJAN SURESH NATARAJAN·Filed 2012·Granted Aug 26, 2014·9 cites·20 claims
- 2682US8949519B2Simulating a memory circuitRAJAN SURESH NATARAJAN·Filed 2009·Granted Feb 3, 2015·11 cites·20 claims
- 2767US9542353B2System and method for reducing command scheduling constraints of memory circuitsRAJAN SURESH NATARAJAN·Filed 2007·Granted Jan 10, 2017·5 cites·14 claims
- 2867US8972673B2Power management of memory circuits by virtual memory simulationRAJAN SURESH NATARAJAN·Filed 2012·Granted Mar 3, 2015·2 cites·14 claims
- 2964US9542352B2System and method for reducing command scheduling constraints of memory circuitsRAJAN SURESH NATARAJAN·Filed 2007·Granted Jan 10, 2017·2 cites·18 claims
- 3053US9632929B2Translating an address associated with a command communicated between a system and memory circuitsRAJAN SURESH NATARAJAN·Filed 2007·Granted Apr 25, 2017·0 cites·19 claims
- 3143US2013188424A1System and method for storing at least a portion of information received in association with a first operation for use in performing a second operationRAJAN SURESH NATARAJAN·Filed 2012·Application pending·0 cites
- 3243US2012109621A1System and Method for Simulating an Aspect of a Memory CircuitRAJAN SURESH NATARAJAN·Filed 2012·Application pending·0 cites
- 3342US9047976B2Combined signal delay and power saving for use with a plurality of memory circuitsRAJAN SURESH NATARAJAN·Filed 2006·Granted Jun 2, 2015·0 cites·24 claims
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