Assignee
SHEN XIAOWEI
US·9 granted patents·1 pending application·36 citations·filing 2006–2011
Top patents by PatentIndex Score
10 records- 0187US8140764B2System for reconfiguring cache memory having an access bit associated with a sector of a lower-level cache memory and a granularity bit associated with a sector of a higher-level cache memorySHEN XIAOWEI·Filed 2011·Granted Mar 20, 2012·9 cites·3 claims
- 0276US8140828B2Handling transaction buffer overflow in multiprocessor by re-executing after waiting for peer processors to complete pending transactions and bypassing the bufferSHEN XIAOWEI·Filed 2008·Granted Mar 20, 2012·8 cites·19 claims
- 0373US8671248B2Architecture support of memory access coloringSHEN XIAOWEI·Filed 2007·Granted Mar 11, 2014·6 cites·18 claims
- 0471US8190824B2Cache line replacement monitoring and profilingSHEN XIAOWEI·Filed 2008·Granted May 29, 2012·4 cites·31 claims
- 0569US8166255B2Reservation required transactionsSHEN XIAOWEI·Filed 2011·Granted Apr 24, 2012·2 cites·8 claims
- 0665US8799581B2Cache coherence monitoring and feedbackSHEN XIAOWEI·Filed 2007·Granted Aug 5, 2014·3 cites·17 claims
- 0763US9141547B2Architecture support of best-effort atomic transactions for multiprocessor systemsSHEN XIAOWEI·Filed 2008·Granted Sep 22, 2015·2 cites·6 claims
- 0861US8789028B2Memory access monitoringSHEN XIAOWEI·Filed 2006·Granted Jul 22, 2014·2 cites·11 claims
- 0950US8131938B2Adaptive mechanisms and methods for supplying volatile data copies in multiprocessor systemsSHEN XIAOWEI·Filed 2008·Granted Mar 6, 2012·0 cites·12 claims
- 1044US2008082756A1Mechanisms and methods of using self-reconciled data to reduce cache coherence overhead in multiprocessor systemsSHEN XIAOWEI·Filed 2006·Application pending·0 cites
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