Assignee
SRINIVASAN SRIKANTH T
US·2 granted patents·1 pending application·0 citations·filing 2011–2013
Technology mixG06F3
Top patents by PatentIndex Score
3 records- 0140US10235180B2Scheduler implementing dependency matrix having restricted entriesSRINIVASAN SRIKANTH T·Filed 2012·Granted Mar 19, 2019·0 cites·7 claims
- 0240US9652236B2Instruction and logic for non-blocking register reclamationSRINIVASAN SRIKANTH T·Filed 2013·Granted May 16, 2017·0 cites·15 claims
- 0329US2013339689A1Later stage read port reductionSRINIVASAN SRIKANTH T·Filed 2011·Application pending·0 cites
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