Assignee
STEIGERWALD JOSEPH M
US·2 granted patents·2 pending applications·15 citations·filing 2006–2009
Top patents by PatentIndex Score
4 records- 0181US8334184B2Polish to remove topography in sacrificial gate layer prior to gate patterningSTEIGERWALD JOSEPH M·Filed 2009·Granted Dec 18, 2012·10 cites·17 claims
- 0272US8441097B2Methods to form memory devices having a capacitor with a recessed electrodeSTEIGERWALD JOSEPH M·Filed 2009·Granted May 14, 2013·5 cites·12 claims
- 0348US2006169409A1Electrochemically polishing conductive films on semiconductor wafersSTEIGERWALD JOSEPH M·Filed 2006·Application pending·0 cites
- 0441US2011147831A1Method for replacement metal gate fillSTEIGERWALD JOSEPH M·Filed 2009·Application pending·0 cites
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