Assignee
SU CHAO-YUAN
TW·3 granted patents·5 pending applications·7 citations·filing 2004–2012
Top patents by PatentIndex Score
8 records- 0176US8624346B2Exclusion zone for stress-sensitive circuit designSU CHAO-YUAN·Filed 2006·Granted Jan 7, 2014·4 cites·23 claims
- 0274US8124458B2Method for packaging semiconductor dies having through-silicon viasSU CHAO-YUAN·Filed 2010·Granted Feb 28, 2012·3 cites·20 claims
- 0351US8629563B2Method for packaging semiconductor dies having through-silicon viasSU CHAO-YUAN·Filed 2012·Granted Jan 14, 2014·0 cites·20 claims
- 0442US2008203566A1Stress buffer layer for packaging processSU CHAO-YUAN·Filed 2007·Application pending·0 cites
- 0538US2006043556A1Stacked packaging methods and structuresSU CHAO-YUAN·Filed 2004·Application pending·0 cites
- 0638US2008246147A1Novel substrate design for semiconductor deviceSU CHAO-YUAN·Filed 2007·Application pending·0 cites
- 0738US2006073635A1Three dimensional package type stacking for thinner package applicationSU CHAO-YUAN·Filed 2004·Application pending·0 cites
- 0837US2006170114A1Novel method for copper wafer wire bondingSU CHAO-YUAN·Filed 2005·Application pending·0 cites
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Counts cover granted patents and pending applications in the PatentIndex corpus. How scoring works →