Assignee
SU TING CHIEH
CN·3 granted patents·5 citations·filing 2006–2010
Technology mixH10D3
Top patents by PatentIndex Score
3 records- 0166US8686507B2System and method for I/O ESD protection with floating and/or biased polysilicon regionsSU TING CHIEH·Filed 2006·Granted Apr 1, 2014·5 cites·12 claims
- 0246US8283726B2System and method for I/O ESD protection with polysilicon regions fabricated by processes for making core transistorsSU TING CHIEH·Filed 2009·Granted Oct 9, 2012·0 cites·10 claims
- 0333US8319286B2System and method for input pin ESD protection with floating and/or biased polysilicon regionsSU TING CHIEH·Filed 2010·Granted Nov 27, 2012·0 cites·10 claims
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