Assignee
SYNOPSYS INC
US·2,017 granted patents·185 pending applications·27,075 citations·filing 1991–2025
Top patents by PatentIndex Score
2,202 records- 0199US7960232B2Methods of designing an integrated circuit on corrugated substrateSYNOPSYS INC·Filed 2009·Granted Jun 14, 2011·139 cites·23 claims
- 0299US7528465B2Integrated circuit on corrugated substrateSYNOPSYS INC·Filed 2007·Granted May 5, 2009·347 cites·4 claims
- 0399US7509621B2Method and apparatus for placing assist features by identifying locations of constructive and destructive interferenceSYNOPSYS INC·Filed 2005·Granted Mar 24, 2009·222 cites·15 claims
- 0499US7265008B2Method of IC production using corrugated substrateSYNOPSYS INC·Filed 2005·Granted Sep 4, 2007·349 cites·18 claims
- 0599US7247887B2Segmented channel MOS transistorSYNOPSYS INC·Filed 2005·Granted Jul 24, 2007·476 cites·30 claims
- 0699US7190050B2Integrated circuit on corrugated substrateSYNOPSYS INC·Filed 2005·Granted Mar 13, 2007·423 cites·14 claims
- 0799US7132203B2Phase shift masking for complex patterns with proximity adjustmentsSYNOPSYS INC·Filed 2004·Granted Nov 7, 2006·228 cites·34 claims
- 0899US7028285B2Standard cell design incorporating phase informationSYNOPSYS INC·Filed 2002·Granted Apr 11, 2006·262 cites·31 claims
- 0999US6978436B2Design data format and hierarchy management for phase processingSYNOPSYS INC·Filed 2002·Granted Dec 20, 2005·207 cites·6 claims
- 1099US6968527B2High yield reticle with proximity effect halosSYNOPSYS INC·Filed 2003·Granted Nov 22, 2005·217 cites·30 claims
- 1199US6918104B2Dissection of printed edges from a fabrication layout for correcting proximity effectsSYNOPSYS INC·Filed 2003·Granted Jul 12, 2005·215 cites·33 claims
- 1298US9953990B1One-time programmable memory using rupturing of gate insulationSYNOPSYS INC·Filed 2017·Granted Apr 24, 2018·21 cites·18 claims
- 1398US9471746B2Sub-resolution assist feature implementation with shot optimizationSYNOPSYS INC·Filed 2015·Granted Oct 18, 2016·23 cites·38 claims
- 1498US7605449B2Enhanced segmented channel MOS transistor with high-permittivity dielectric isolation materialSYNOPSYS INC·Filed 2007·Granted Oct 20, 2009·336 cites·18 claims
- 1598US7508031B2Enhanced segmented channel MOS transistor with narrowed base regionsSYNOPSYS INC·Filed 2007·Granted Mar 24, 2009·343 cites·21 claims
- 1698US7509622B2Dummy filling technique for improved planarization of chip surface topographySYNOPSYS INC·Filed 2006·Granted Mar 24, 2009·243 cites·29 claims
- 1798US7312003B2Design and layout of phase shifting photolithographic masksSYNOPSYS INC·Filed 2004·Granted Dec 25, 2007·116 cites·5 claims
- 1898US7194712B2Method and apparatus for identifying line-end features for lithography verificationSYNOPSYS INC·Filed 2004·Granted Mar 20, 2007·222 cites·24 claims
- 1998US7122281B2Critical dimension control using full phase and trim masksSYNOPSYS INC·Filed 2002·Granted Oct 17, 2006·142 cites·17 claims
- 2097US11641194B1Single flux quantum inverter circuitSYNOPSYS INC·Filed 2020·Granted May 2, 2023·9 cites·18 claims
- 2197US11061321B1Obtaining a mask using a cost function gradient from a Jacobian matrix generated from a perturbation look-up tableSYNOPSYS INC·Filed 2020·Granted Jul 13, 2021·9 cites·20 claims
- 2297US10777288B2One time programmable (OTP) bit cell with integrated inhibit deviceSYNOPSYS INC·Filed 2019·Granted Sep 15, 2020·16 cites·22 claims
- 2397US8924908B2FinFET cell architecture with power tracesSYNOPSYS INC·Filed 2013·Granted Dec 30, 2014·23 cites·22 claims
- 2497US7926018B2Method and apparatus for generating a layout for a transistorSYNOPSYS INC·Filed 2007·Granted Apr 12, 2011·108 cites·19 claims
- 2597US7895548B2Filler cells for design optimization in a place-and-route systemSYNOPSYS INC·Filed 2007·Granted Feb 22, 2011·128 cites·34 claims
- 2697US7454731B2Generation of engineering change order (ECO) constraints for use in selecting ECO repair techniquesSYNOPSYS INC·Filed 2006·Granted Nov 18, 2008·216 cites·15 claims
- 2797US7421678B2Assist feature placement using a process-sensitivity modelSYNOPSYS INC·Filed 2006·Granted Sep 2, 2008·200 cites·18 claims
- 2897US6950974B1Efficient compression and application of deterministic patterns in a logic BIST architectureSYNOPSYS INC·Filed 2001·Granted Sep 27, 2005·92 cites·30 claims
- 2997US6873720B2System and method of providing mask defect printability analysisSYNOPSYS INC·Filed 2001·Granted Mar 29, 2005·112 cites·54 claims
- 3096US11342919B1Complementary asynchronous single flux quantum circuitsSYNOPSYS INC·Filed 2020·Granted May 24, 2022·6 cites·20 claims
- 3196US10755026B1Circuit design including design rule violation correction utilizing patches based on deep reinforcement learningSYNOPSYS INC·Filed 2018·Granted Aug 25, 2020·40 cites·20 claims
- 3296US9684743B2Isolated debugging in an FPGA based emulation environmentSYNOPSYS INC·Filed 2015·Granted Jun 20, 2017·21 cites·20 claims
- 3396US7900105B2Dynamically reconfigurable shared scan-in test architectureSYNOPSYS INC·Filed 2010·Granted Mar 1, 2011·15 cites·35 claims
- 3496US7827510B1Enhanced hardware debugging with embedded FPGAS in a hardware description languageSYNOPSYS INC·Filed 2007·Granted Nov 2, 2010·88 cites·45 claims
- 3596US7823034B2Pipeline of additional storage elements to shift input/output data of combinational scan compression circuitSYNOPSYS INC·Filed 2007·Granted Oct 26, 2010·41 cites·15 claims
- 3696US7484198B2Managing integrated circuit stress using dummy diffusion regionsSYNOPSYS INC·Filed 2006·Granted Jan 27, 2009·48 cites·8 claims
- 3796US7237162B1Deterministic BIST architecture tolerant of uncertain scan chain outputsSYNOPSYS INC·Filed 2002·Granted Jun 26, 2007·69 cites·12 claims
- 3896US7159197B2Shape-based geometry engine to perform smoothing and other layout beautification operationsSYNOPSYS INC·Filed 2001·Granted Jan 2, 2007·294 cites·54 claims
- 3996US6928635B2Selectively applying resolution enhancement techniques to improve performance and manufacturing cost of integrated circuitsSYNOPSYS INC·Filed 2002·Granted Aug 9, 2005·236 cites·18 claims
- 4096US5754826ACAD and simulation system for targeting IC designs to multiple fabrication processesSYNOPSYS INC·Filed 1995·Granted May 19, 1998·374 cites·18 claims
- 4195US11984384B2Power routing for 2.5D or 3D integrated circuits including a buried power rail and interposer with power delivery networkSYNOPSYS INC·Filed 2021·Granted May 14, 2024·2 cites·13 claims
- 4295US11636388B1Machine learning-based algorithm to accurately predict detail-route DRVS for efficient design closure at advanced technology nodesSYNOPSYS INC·Filed 2020·Granted Apr 25, 2023·11 cites·29 claims
- 4395US11233516B1Single flux quantum circuit that includes a sequencing circuitSYNOPSYS INC·Filed 2020·Granted Jan 25, 2022·5 cites·19 claims
- 4495US10635776B1Producing mask layouts with rounded cornersSYNOPSYS INC·Filed 2018·Granted Apr 28, 2020·8 cites·19 claims
- 4595US10318697B2Sub-resolution assist feature implementation for shot generationSYNOPSYS INC·Filed 2016·Granted Jun 11, 2019·6 cites·28 claims
- 4695US10312229B2Memory cells including vertical nanowire transistorsSYNOPSYS INC·Filed 2017·Granted Jun 4, 2019·16 cites·36 claims
- 4795US9747407B2Categorized stitching guidance for triple-patterning technologySYNOPSYS INC·Filed 2015·Granted Aug 29, 2017·12 cites·18 claims
- 4895US9740811B2Virtual hierarchical layer patterningSYNOPSYS INC·Filed 2015·Granted Aug 22, 2017·16 cites·30 claims
- 4995US9727675B2Parameter extraction of DFTSYNOPSYS INC·Filed 2016·Granted Aug 8, 2017·14 cites·24 claims
- 5095US9547740B2Methods for fabricating high-density integrated circuit devicesSYNOPSYS INC·Filed 2014·Granted Jan 17, 2017·17 cites·15 claims
Showing the top 50 of 2,202 patent records by PatentIndex Score.
Counts cover granted patents and pending applications in the PatentIndex corpus. How scoring works →