Assignee
SYNPLICITY INC
US·55 granted patents·2,970 citations·filing 1998–2005
Top patents by PatentIndex Score
55 records- 0198US7366997B1Methods and apparatuses for thermal analysis based circuit designSYNPLICITY INC·Filed 2005·Granted Apr 29, 2008·288 cites·33 claims
- 0298US6618839B1Method and system for providing an electronic system design with enhanced debugging capabilitiesSYNPLICITY INC·Filed 2000·Granted Sep 9, 2003·195 cites·35 claims
- 0398US6581191B1Hardware debugging in a hardware description languageSYNPLICITY INC·Filed 2000·Granted Jun 17, 2003·227 cites·41 claims
- 0495US7240303B1Hardware/software co-debugging in a hardware description languageSYNPLICITY INC·Filed 2003·Granted Jul 3, 2007·132 cites·57 claims
- 0594US7213216B2Method and system for debugging using replicated logic and trigger logicSYNPLICITY INC·Filed 2005·Granted May 1, 2007·26 cites·15 claims
- 0694US7093204B2Method and apparatus for automated synthesis of multi-channel circuitsSYNPLICITY INC·Filed 2003·Granted Aug 15, 2006·75 cites·42 claims
- 0794US6823497B2Method and user interface for debugging an electronic systemSYNPLICITY INC·Filed 2002·Granted Nov 23, 2004·170 cites·41 claims
- 0894US6734472B2Power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing in integrated circuit deviceSYNPLICITY INC·Filed 2002·Granted May 11, 2004·77 cites·20 claims
- 0993US7200822B1Circuits with modular redundancy and methods and apparatuses for their automated synthesisSYNPLICITY INC·Filed 2004·Granted Apr 3, 2007·59 cites·135 claims
- 1093US7072818B1Method and system for debugging an electronic systemSYNPLICITY INC·Filed 2000·Granted Jul 4, 2006·94 cites·46 claims
- 1192US6711729B1Methods and apparatuses for designing integrated circuits using automatic reallocation techniquesSYNPLICITY INC·Filed 2000·Granted Mar 23, 2004·109 cites·80 claims
- 1292US6668364B2Methods and apparatuses for designing integrated circuitsSYNPLICITY INC·Filed 2002·Granted Dec 23, 2003·63 cites·48 claims
- 1390US7069526B2Hardware debugging in a hardware description languageSYNPLICITY INC·Filed 2004·Granted Jun 27, 2006·46 cites·33 claims
- 1490US7065481B2Method and system for debugging an electronic system using instrumentation circuitry and a logic analyzerSYNPLICITY INC·Filed 2002·Granted Jun 20, 2006·59 cites·27 claims
- 1590US6904576B2Method and system for debugging using replicated logicSYNPLICITY INC·Filed 2002·Granted Jun 7, 2005·35 cites·27 claims
- 1690US6438735B1Methods and apparatuses for designing integrated circuitsSYNPLICITY INC·Filed 1999·Granted Aug 20, 2002·118 cites·104 claims
- 1788US7278120B2Methods and apparatuses for transient analyses of circuitsSYNPLICITY INC·Filed 2004·Granted Oct 2, 2007·45 cites·51 claims
- 1888US7237214B1Method and apparatus for circuit partitioning and trace assignment in circuit designSYNPLICITY INC·Filed 2004·Granted Jun 26, 2007·37 cites·27 claims
- 1988US6904577B2Hardware debugging in a hardware description languageSYNPLICITY INC·Filed 2003·Granted Jun 7, 2005·41 cites·73 claims
- 2088US6449762B1Maintaining correspondence between text and schematic representations of circuit elements in circuit synthesisSYNPLICITY INC·Filed 1999·Granted Sep 10, 2002·135 cites·31 claims
- 2187US6931572B1Design instrumentation circuitrySYNPLICITY INC·Filed 2000·Granted Aug 16, 2005·35 cites·21 claims
- 2286US7178118B2Method and apparatus for automated circuit designSYNPLICITY INC·Filed 2004·Granted Feb 13, 2007·41 cites·63 claims
- 2386US7007254B1Method and apparatus for the design and analysis of digital circuits with time division multiplexingSYNPLICITY INC·Filed 2003·Granted Feb 28, 2006·34 cites·36 claims
- 2486US6687882B1Methods and apparatuses for non-equivalence checking of circuits with subspaceSYNPLICITY INC·Filed 2002·Granted Feb 3, 2004·44 cites·33 claims
- 2584US7398445B2Method and system for debug and test using replicated logicSYNPLICITY INC·Filed 2005·Granted Jul 8, 2008·13 cites·19 claims
- 2684US6519754B1Methods and apparatuses for designing integrated circuitsSYNPLICITY INC·Filed 1999·Granted Feb 11, 2003·81 cites·73 claims
- 2783US7251800B2Method and apparatus for automated circuit designSYNPLICITY INC·Filed 2004·Granted Jul 31, 2007·45 cites·76 claims
- 2883US6735743B1Method and apparatus for invalid state detectionSYNPLICITY INC·Filed 2001·Granted May 11, 2004·30 cites·84 claims
- 2983US6643829B1Reducing clock skew in clock gating circuitsSYNPLICITY INC·Filed 2001·Granted Nov 4, 2003·35 cites·15 claims
- 3082US7356786B2Method and user interface for debugging an electronic systemSYNPLICITY INC·Filed 2004·Granted Apr 8, 2008·30 cites·20 claims
- 3182US7217887B2Power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing in integrated circuit deviceSYNPLICITY INC·Filed 2004·Granted May 15, 2007·24 cites·10 claims
- 3282US6973632B1Method and apparatus to estimate delay for logic circuit optimizationSYNPLICITY INC·Filed 2002·Granted Dec 6, 2005·39 cites·72 claims
- 3381US7350173B1Method and apparatus for placement and routing cells on integrated circuit chipsSYNPLICITY INC·Filed 2003·Granted Mar 25, 2008·35 cites·18 claims
- 3481US7222315B2Hardware-based HDL code coverage and design analysisSYNPLICITY INC·Filed 2003·Granted May 22, 2007·31 cites·80 claims
- 3580US7010769B2Methods and apparatuses for designing integrated circuitsSYNPLICITY INC·Filed 2002·Granted Mar 7, 2006·21 cites·99 claims
- 3679US7162704B2Method and apparatus for circuit design and retimingSYNPLICITY INC·Filed 2003·Granted Jan 9, 2007·20 cites·27 claims
- 3779US6389586B1Method and apparatus for invalid state detectionSYNPLICITY INC·Filed 1999·Granted May 14, 2002·68 cites·1 claims
- 3878US6691286B1Methods and apparatuses for checking equivalence of circuitsSYNPLICITY INC·Filed 2001·Granted Feb 10, 2004·29 cites·46 claims
- 3978US6618835B1Transforming a circuit having loop structure and tri-state element using replicationSYNPLICITY INC·Filed 2001·Granted Sep 9, 2003·28 cites·30 claims
- 4078US6182268B1Methods and apparatuses for automatic extraction of finite state machinesSYNPLICITY INC·Filed 1998·Granted Jan 30, 2001·80 cites·26 claims
- 4177US7275233B2Methods and apparatuses for designing integrated circuitsSYNPLICITY INC·Filed 2003·Granted Sep 25, 2007·17 cites·105 claims
- 4276US7376919B1Methods and apparatuses for automated circuit optimization and verificationSYNPLICITY INC·Filed 2005·Granted May 20, 2008·7 cites·28 claims
- 4375US7082582B1Reducing clock skew in clock gating circuitsSYNPLICITY INC·Filed 2003·Granted Jul 25, 2006·19 cites·30 claims
- 4475US6519742B1Local naming for HDL compilationSYNPLICITY INC·Filed 2000·Granted Feb 11, 2003·27 cites·62 claims
- 4572US6836420B1Method and apparatus for resetable memory and design approach for sameSYNPLICITY INC·Filed 2002·Granted Dec 28, 2004·13 cites·20 claims
- 4671US6978430B2Methods and apparatuses for designing integrated circuitsSYNPLICITY INC·Filed 2003·Granted Dec 20, 2005·11 cites·45 claims
- 4769US7117463B2Verification of digital circuitry using range generatorsSYNPLICITY INC·Filed 2002·Granted Oct 3, 2006·15 cites·108 claims
- 4869US6807556B1Method and apparatus for parallel carry chainsSYNPLICITY INC·Filed 2000·Granted Oct 19, 2004·12 cites·63 claims
- 4967US7263673B1Method and apparatus for automated synthesis and optimization of datapathsSYNPLICITY INC·Filed 2004·Granted Aug 28, 2007·13 cites·45 claims
- 5066US7051296B1Method and apparatus for parallel carry chainsSYNPLICITY INC·Filed 2004·Granted May 23, 2006·10 cites·12 claims
Showing the top 50 of 55 patent records by PatentIndex Score.
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