Assignee
THAYER LARRY J
US·6 granted patents·3 pending applications·37 citations·filing 2005–2011
Top patents by PatentIndex Score
9 records- 0187US8634221B2Memory system that utilizes a wide input/output (I/O) interface to interface memory storage with an interposer and that utilizes a SerDes interface to interface a memory controller with an integrated circuit, and a methodTHAYER LARRY J·Filed 2011·Granted Jan 21, 2014·8 cites·25 claims
- 0282US9298668B2Bit error rate reduction buffer, method and apparatusTHAYER LARRY J·Filed 2010·Granted Mar 29, 2016·5 cites·5 claims
- 0374US8554991B2High speed interface for dynamic random access memory (DRAM)THAYER LARRY J·Filed 2011·Granted Oct 8, 2013·5 cites·14 claims
- 0473US8612797B2Systems and methods of selectively managing errors in memory modulesTHAYER LARRY J·Filed 2006·Granted Dec 17, 2013·11 cites·20 claims
- 0569US8914683B2Repairing high-speed serial linksTHAYER LARRY J·Filed 2008·Granted Dec 16, 2014·4 cites·13 claims
- 0660US8886892B2Memory module and method employing a multiplexer to replace a memory deviceTHAYER LARRY J·Filed 2007·Granted Nov 11, 2014·4 cites·20 claims
- 0742US2006236158A1Memory element for mitigating soft errors in logicTHAYER LARRY J·Filed 2005·Application pending·0 cites
- 0842US2006248355A1Power throttling system and method for a memory controllerTHAYER LARRY J·Filed 2005·Application pending·0 cites
- 0942US2007094569A1Determining hard errors vs. soft errors in memoryTHAYER LARRY J·Filed 2005·Application pending·0 cites
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