Assignee
TOPACIO RODEN
CA·8 granted patents·1 pending application·49 citations·filing 2008–2014
Top patents by PatentIndex Score
9 records- 0194US8227926B2Routing layer for mitigating stress in a semiconductor dieTOPACIO RODEN·Filed 2009·Granted Jul 24, 2012·28 cites·27 claims
- 0289US8299632B2Routing layer for mitigating stress in a semiconductor dieTOPACIO RODEN·Filed 2011·Granted Oct 30, 2012·9 cites·19 claims
- 0386US9059159B2Routing layer for mitigating stress in a semiconductor dieTOPACIO RODEN·Filed 2013·Granted Jun 16, 2015·6 cites·15 claims
- 0469US8313984B2Die substrate with reinforcement structureTOPACIO RODEN·Filed 2008·Granted Nov 20, 2012·4 cites·18 claims
- 0562US10431533B2Circuit board with constrained solder interconnect padsTOPACIO RODEN·Filed 2014·Granted Oct 1, 2019·1 cites·20 claims
- 0661US8927344B2Die substrate with reinforcement structureTOPACIO RODEN·Filed 2012·Granted Jan 6, 2015·1 cites·20 claims
- 0754US8633599B2Semiconductor chip with underfill anchorsTOPACIO RODEN·Filed 2013·Granted Jan 21, 2014·0 cites·18 claims
- 0853US8642463B2Routing layer for mitigating stress in a semiconductor dieTOPACIO RODEN·Filed 2012·Granted Feb 4, 2014·0 cites·3 claims
- 0946US2011100692A1Circuit Board with Variable Topography Solder InterconnectsTOPACIO RODEN·Filed 2009·Application pending·0 cites
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