Assignee
WANG LAUNG-TERNG
US·9 granted patents·1 pending application·92 citations·filing 2009–2012
Top patents by PatentIndex Score
10 records- 0197US8522096B2Method and apparatus for testing 3D integrated circuitsWANG LAUNG-TERNG·Filed 2011·Granted Aug 27, 2013·38 cites·36 claims
- 0290US8458544B2Multiple-capture DFT system to reduce peak capture power during self-test or scan testWANG LAUNG-TERNG·Filed 2011·Granted Jun 4, 2013·7 cites·6 claims
- 0389US8219945B2Computer-aided design system to automate scan synthesis at register-transfer levelWANG LAUNG-TERNG·Filed 2011·Granted Jul 10, 2012·5 cites·4 claims
- 0486US8667451B2Method and apparatus for broadcasting scan patterns in a scan-based integrated circuitWANG LAUNG-TERNG·Filed 2012·Granted Mar 4, 2014·4 cites·12 claims
- 0586US8161441B2Robust scan synthesis for protecting soft errorsWANG LAUNG-TERNG·Filed 2009·Granted Apr 17, 2012·14 cites·16 claims
- 0685US8418100B2Robust scan synthesis for protecting soft errorsWANG LAUNG-TERNG·Filed 2012·Granted Apr 9, 2013·6 cites·16 claims
- 0780US8949299B2Method and apparatus for hybrid ring generator designWANG LAUNG-TERNG·Filed 2011·Granted Feb 3, 2015·6 cites·16 claims
- 0880US8091002B2Multiple-capture DFT system to reduce peak capture power during self-test or scan testWANG LAUNG-TERNG·Filed 2010·Granted Jan 3, 2012·4 cites·6 claims
- 0977US8402328B2Apparatus and method for protecting soft errorsWANG LAUNG-TERNG·Filed 2009·Granted Mar 19, 2013·8 cites·50 claims
- 1040US2010138709A1Method and apparatus for delay fault coverage enhancementWANG LAUNG-TERNG·Filed 2009·Application pending·0 cites
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