Inventor

KUO NAI-PING

TW53 patents

⚠️ This page may combine multiple inventors who share the name “KUO NAI-PING”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KUO NAI-PING

MACRONIX INT CO LTD

Method for adjusting a reference current of a flash nitride read only memory (NROM) and device thereof

Dual reference cell sensing scheme for non-volatile memory

Apparatus and method for detecting word line leakage in memory devices

Apparatus and method for detecting word line leakage in memory devices

Memory array architecture

Retention logic for non-volatile memory

Memory device having a virtual ground array and methods using program algorithm to improve read margin loss

Systems and methods for using a single reference cell in a dual bit flash memory

Apparatus and system for reading non-volatile memory with dual reference cells

Memory device with a plurality of reference cells on a bit line

ECC method for flash memory

Memory system and operating method thereof

Memory device and operating method of same

Low latency memory erase suspend operation

Memory device including risky mapping table and controlling method thereof

Apparatus and method for detecting word line leakage in memory devices

Structures and methods for enhancing erase uniformity in an NROM array

System and method for over erase reduction of nitride read only memory

Semiconductor device including memory cells and current limiter

Read source line compensation in a non-volatile memory

Memory system having planes with multibit status

Memory supporting multiple types of operations

Method and device for reading a memory

Method, electronic device and controller for recovering array of memory cells

Retention logic for non-volatile memory

Method, electronic device and controller for recovering memory array

Non-volatile memory device and method for shortened erase operation during testing

Method and apparatus of changing device identification codes of a memory integrated circuit device

Method and apparatus for leakage suppression in flash memory in response to external commands

Apparatus and method to tolerate floating input pin for input buffer

Method and apparatus for protection of non-volatile memory in presence of out-of-specification operating voltage

Structures and methods for enhancing erase uniformity in a nitride read-only memory array

System and method for over erase reduction of nitride read only memory

Solid state disk, data transmitting method and intermediary controller to support reduced SSD controller pad count

Memory device and method for managing read counts of memory device

Method and system for operating memory

Memory device and management method thereof

HUNG CHUN-HSIUNG

Method and apparatus for shortened erase operation

Apparatus and method to tolerate floating input pin for input buffer

Method and apparatus for repairing memory

KUO NAI-PING

Method and apparatus for leakage suppression in flash memory

Method and apparatus for leakage suppression in flash memory in response to external commands

Method and apparatus of changing device identification codes of a memory integrated circuit device

LIN YUNG FENG

Non-volatile memory device and charge pump circuit for the same

Non-volatile memory device and charge pump circuit for the same

HSIEH WEN-YI

Memory devices and methods using improved reference cell trimming algorithms for accurate read operation window control

CHAUNG YU-MENG

Memory apparatus

MACRONIZ INTERNAT CO LTD

Method and structure for testing embedded flash memory

HUNG CHUN HSIUNG

Method and apparatus for protection of non-volatile memory in presence of out-of-specification operating voltage

CHANG KUEN-LONG

Data protecting method capable of effectively recording protection information and memory using thereof