Inventor

KESSLER RICHARD E

US122 patents

⚠️ This page may combine multiple inventors who share the name “KESSLER RICHARD E”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KESSLER RICHARD E

HEWLETT PACKARD DEVELOPMENT CO

Computer architecture and system for efficient management of bi-directional bus

Scalable directory based cache coherence protocol

Mechanism to control the allocation of an N-source shared buffer

Special encoding of known bad data

Broadcast invalidate scheme

Scalable efficient I/O port protocol

System for minimizing memory bank conflicts in a computer system

Efficient translation lookaside buffer miss processing in computer systems with a large range of page sizes

Fast lane prefetching

Efficient address interleaving with simultaneous multiple locality options

Fault containment and error recovery in a scalable multiprocessor

Speculative directory writes in a directory based cache coherent nonuniform memory access protocol

Broadcast invalidate scheme

Priority rules for reducing network message routing latency

Computer resource management and allocation system

Fault containment and error recovery in a scalable multiprocessor

Special encoding of known bad data

Mechanism for synchronizing multiple skewed source-synchronous data channels with automatic initialization feature

CAVIUM NETWORKS INC

Selective replication of data structures

Method and apparatus for reducing host overhead in a socket server implementation

TCP engine

Packet queuing, scheduling and ordering

Apparatus and method for data deskew

Method and apparatus for reducing host overhead in a socket server implementation

Store instruction ordering for multi-core processor

Direct access to low-latency memory

Transparent IPSec processing inline between a framer and a network component

Method and apparatus for establishing secure sessions

CRAY RESEARCH INC

Massively parallel processing system using two data paths: one connecting router circuit to the interconnect network and the other connecting router circuit to I/O controller

Messaging in distributed memory multiprocessing system having shell circuitry for atomic control of message storage queue&#39;s tail pointer structure in local memory

Stream buffers for high-performance computer memory system

Barrier and eureka synchronization architecture for multiprocessors

System for allocating messages between virtual channels to avoid deadlock and to optimize the amount of message traffic on each type of virtual channel

Using external registers to extend memory reference capabilities of a microprocessor

Networked multiprocessor system with global distributed memory and block transfer engine

Multiprocessor computer system with interleaved processing element nodes

Method of handling arbitrary size message queues in which a message is written into an aligned block of external registers within a plurality of external registers

CAVIUM INC

System and method to provide non-coherent access to a coherent memory system

Translation bypass in multi-stage address translation

System and method to reduce memory access latencies using selective replication across multiple memory ports

Method and apparatus for estimating overshoot power after estimating power of executing events

COMPAQ INFORMATION TECHNOLOGIE

Method and apparatus for performing speculative memory fills into a microprocessor

Method and apparatus for developing multiprocessor cache control protocols by presenting a clean victim signal to an external system

Proprammable DRAM address mapping mechanism

BOUCHARD GREGG A

Deterministic finite automata (DFA) processing

Deterministic finite automata (DFA) instruction

CAVIUM NETWORKS

Interface for a security coprocessor

IPsec performance optimization

SILICON GRAPHICS INC

System and method for fast barrier synchronization

COMPAQ COMPUTER CORP

Method and apparatus for minimizing dcache index match aliasing using hashing in synonym/subset processing

Messaging in distributed memory multiprocessing system having shell circuitry for atomic control of message storage queue's tail pointer structure in local memory