P

Inventor

COWPERTHWAITE DAVID J

US37 patents
⚠️ This page may combine multiple inventors who share the name “COWPERTHWAITE DAVID J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

INTEL CORP

25 patents
US10380039B2Aug 13, 2019

Apparatus and method for memory management in a graphics processing environment

INTEL CORP17 citations94
US10043232B1Aug 7, 2018

Compute cluster preemption within a general-purpose graphics processing unit

INTEL CORP22 citations94
US7340677B2Mar 4, 2008

Methods and apparatuses of presenting categorical programs in progressive levels of content details

INTEL CORP33 citations92
US10482562B2Nov 19, 2019

Graphics engine partitioning mechanism

INTEL CORP8 citations84
US7971203B2Jun 28, 2011

Method, apparatus and system for dynamically reassigning a physical device from one virtual machine to another

INTEL CORP12 citations84
US7644407B2Jan 5, 2010

Method, apparatus and system for seamlessly sharing a graphics device amongst virtual machines

INTEL CORP16 citations84
US7454756B2Nov 18, 2008

Method, apparatus and system for seamlessly sharing devices amongst virtual machines

INTEL CORP14 citations84
US7809161B2Oct 5, 2010

Method and apparatus for three-dimensional tracking of infra-red beacons

INTEL CORP4 citations74
US7310441B2Dec 18, 2007

Method and apparatus for three-dimensional tracking of infra-red beacons

INTEL CORP4 citations74
US11360914B2Jun 14, 2022

Apparatus and method for memory management in a graphics processing environment

INTEL CORP1 citations73
US11232536B2Jan 25, 2022

Thread prefetch mechanism

INTEL CORP2 citations73
US10776156B2Sep 15, 2020

Thread priority mechanism

INTEL CORP2 citations73
US10769078B2Sep 8, 2020

Apparatus and method for memory management in a graphics processing environment

INTEL CORP1 citations73
US10496448B2Dec 3, 2019

De-centralized load-balancing at processors

INTEL CORP2 citations73
US10191759B2Jan 29, 2019

Apparatus and method for scheduling graphics processing unit workloads from virtual machines

INTEL CORP5 citations73
US11715174B2Aug 1, 2023

Compute cluster preemption within a general-purpose graphics processing unit

INTEL CORP0 citations63
US11270406B2Mar 8, 2022

Compute cluster preemption within a general-purpose graphics processing unit

INTEL CORP0 citations63
US10565676B2Feb 18, 2020

Thread prefetch mechanism

INTEL CORP1 citations63
US11551400B2Jan 10, 2023

Apparatus and method for optimized tile-based rendering

INTEL CORP1 citations62
US11341600B2May 24, 2022

Graphics engine partitioning mechanism

INTEL CORP0 citations62
US11514550B2Nov 29, 2022

Apparatus and method for display virtualization using mapping between virtual and physical display planes

INTEL CORP0 citations60
US11449396B2Sep 20, 2022

Failover support within a SoC via standby domain

INTEL CORP1 citations56
US10839476B2Nov 17, 2020

Compute cluster preemption within a general-purpose graphics processing unit

INTEL CORP0 citations52
US10460417B2Oct 29, 2019

Compute cluster preemption within a general-purpose graphics processing unit

INTEL CORP0 citations52
US10706493B2Jul 7, 2020

Apparatus and method for display virtualization using mapping between virtual and physical display planes

INTEL CORP0 citations49

IDELIX SOFTWARE INC

5 patents

COWPERTHWAITE DAVID J

3 patents

COORAY NIRANJAN L

1 patent

CEN SHANWEI

1 patent

SAHITA RAVI L

1 patent

BAAR DAVID J P

1 patent