Inventor
MAIYURAN SUBRAMANIAM M
US28 patents
Patents
28 patentsUS10043232B1Aug 7, 2018
Compute cluster preemption within a general-purpose graphics processing unit
INTEL CORP22 citations94
US10387160B2Aug 20, 2019
Shared local memory tiling mechanism
INTEL CORP7 citations84
US11232536B2Jan 25, 2022
Thread prefetch mechanism
INTEL CORP2 citations73
US10725785B2Jul 28, 2020
Shared local memory tiling mechanism
INTEL CORP1 citations73
US10282812B2May 7, 2019
Page faulting and selective preemption
INTEL CORP2 citations73
US10269088B2Apr 23, 2019
Dynamic thread execution arbitration
INTEL CORP3 citations73
US10990409B2Apr 27, 2021
Control flow mechanism for execution of graphics processor instructions using active channel packing
INTEL CORP2 citations71
US12131402B2Oct 29, 2024
Page faulting and selective preemption
INTEL CORP0 citations63
US12067641B2Aug 20, 2024
Page faulting and selective preemption
INTEL CORP0 citations63
US11715174B2Aug 1, 2023
Compute cluster preemption within a general-purpose graphics processing unit
INTEL CORP0 citations63
US11354769B2Jun 7, 2022
Page faulting and selective preemption
INTEL CORP0 citations63
US11270406B2Mar 8, 2022
Compute cluster preemption within a general-purpose graphics processing unit
INTEL CORP0 citations63
US10565676B2Feb 18, 2020
Thread prefetch mechanism
INTEL CORP1 citations63
US11531510B2Dec 20, 2022
Regional adjustment of render rate
INTEL CORP0 citations62
US11508338B2Nov 22, 2022
Register spill/fill using shared local memory space
INTEL CORP0 citations62
US11354768B2Jun 7, 2022
Intelligent graphics dispatching mechanism
INTEL CORP0 citations62
US11163580B2Nov 2, 2021
Shared local memory tiling mechanism
INTEL CORP0 citations62
US11099800B2Aug 24, 2021
Regional adjustment of render rate
INTEL CORP0 citations62
US11537403B2Dec 27, 2022
Control flow mechanism for execution of graphics processor instructions using active channel packing
INTEL CORP0 citations61
US10839476B2Nov 17, 2020
Compute cluster preemption within a general-purpose graphics processing unit
INTEL CORP0 citations52
US10796667B2Oct 6, 2020
Register spill/fill using shared local memory space
INTEL CORP0 citations52
US10726517B2Jul 28, 2020
Page faulting and selective preemption
INTEL CORP0 citations52
US10691392B2Jun 23, 2020
Regional adjustment of render rate
INTEL CORP0 citations52
US10565675B2Feb 18, 2020
Intelligent graphics dispatching mechanism
INTEL CORP0 citations52
US10460417B2Oct 29, 2019
Compute cluster preemption within a general-purpose graphics processing unit
INTEL CORP0 citations52
US10235736B2Mar 19, 2019
Intelligent graphics dispatching mechanism
INTEL CORP0 citations52
US10453427B2Oct 22, 2019
Register spill/fill using shared local memory space
INTEL CORP0 citations51
US9846962B2Dec 19, 2017
Optimizing clipping operations in position only shading tile deferred renderers
INTEL CORP0 citations50