Inventor
RAGHAVAN VIJAYA
US25 patents
⚠️ This page may combine multiple inventors who share the name “RAGHAVAN VIJAYA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
MATHWORKS INC
18 patentsUS7020850B2Mar 28, 2006
Event-based temporal logic
MATHWORKS INC82 citations98
US7720656B2May 18, 2010
Graphical functions
MATHWORKS INC19 citations92
US7433808B1Oct 7, 2008
Event-based temporal logic
MATHWORKS INC19 citations92
US10157045B2Dec 18, 2018
Systems and methods for automatically generating code for deep learning systems
MATHWORKS INC43 citations90
US8364456B2Jan 29, 2013
Conditionally executed states
MATHWORKS INC8 citations84
US7941303B1May 10, 2011
Event-based temporal logic
MATHWORKS INC8 citations84
US9424005B1Aug 23, 2016
Templatized component
MATHWORKS INC13 citations82
US10831456B1Nov 10, 2020
External code integrations within a computing environment
MATHWORKS INC20 citations78
US10318653B1Jun 11, 2019
Systems and methods for creating harness models for model verification
MATHWORKS INC13 citations78
US9507888B1Nov 29, 2016
Active state visualization for finite state machine models
MATHWORKS INC11 citations78
US9594608B2Mar 14, 2017
Message-based modeling
MATHWORKS INC5 citations72
US8904367B1Dec 2, 2014
Auto pipeline insertion
MATHWORKS INC4 citations72
US9600241B2Mar 21, 2017
Unified state transition table describing a state machine model
MATHWORKS INC6 citations70
US10949182B2Mar 16, 2021
Systems and methods for generating code for parallel processing units
MATHWORKS INC5 citations69
US9304840B2Apr 5, 2016
Message-based modeling
MATHWORKS INC1 citations62
US10922208B2Feb 16, 2021
Observer for simulation test and verification
MATHWORKS INC0 citations46
US10360502B2Jul 23, 2019
Generating a state diagram
MATHWORKS INC0 citations39
US10684936B2Jun 16, 2020
Observer for simulation test and verification
MATHWORKS INC0 citations36