P

Inventor

LAURITZEN ANDREW T

CA31 patents
⚠️ This page may combine multiple inventors who share the name “LAURITZEN ANDREW T”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

INTEL CORP

28 patents
US10089230B1Oct 2, 2018

Resource-specific flushes and invalidations of cache and memory fabric structures

INTEL CORP11 citations84
US11748302B2Sep 5, 2023

Engine to enable high speed context switching via on-die storage

INTEL CORP2 citations73
US11210265B2Dec 28, 2021

Engine to enable high speed context switching via on-die storage

INTEL CORP3 citations73
US11120766B2Sep 14, 2021

Graphics with adaptive temporal adjustments

INTEL CORP1 citations73
US11062506B2Jul 13, 2021

Tile-based immediate mode rendering with early hierarchical-z

INTEL CORP3 citations73
US10957050B2Mar 23, 2021

Decoupled multi-layer render frequency

INTEL CORP2 citations73
US10896657B2Jan 19, 2021

Graphics with adaptive temporal adjustments

INTEL CORP3 citations73
US10643374B2May 5, 2020

Positional only shading pipeline (POSH) geometry data processing with coarse Z buffer

INTEL CORP3 citations73
US10489915B2Nov 26, 2019

Decouple multi-layer render fequency

INTEL CORP4 citations73
US10395623B2Aug 27, 2019

Handling surface level coherency without reliance on fencing

INTEL CORP3 citations73
US12399734B2Aug 26, 2025

Engine to enable high speed context switching via on-die storage

INTEL CORP0 citations62
US12271991B2Apr 8, 2025

Topology shader technology

INTEL CORP0 citations62
US12014701B2Jun 18, 2024

Graphics with adaptive temporal adjustments

INTEL CORP0 citations62
US11704856B2Jul 18, 2023

Topology shader technology

INTEL CORP0 citations62
US11461959B2Oct 4, 2022

Positional only shading pipeline (POSH) geometry data processing with coarse Z buffer

INTEL CORP0 citations62
US11195497B2Dec 7, 2021

Handling surface level coherency without reliance on fencing

INTEL CORP0 citations62
US11182948B2Nov 23, 2021

Topology shader technology

INTEL CORP0 citations62
US11182296B2Nov 23, 2021

Memory-based dependency tracking and cache pre-fetch hardware for multi-resolution shading

INTEL CORP0 citations62
US11049214B2Jun 29, 2021

Deferred geometry rasterization technology

INTEL CORP0 citations62
US10957096B2Mar 23, 2021

Topology shader technology

INTEL CORP0 citations62
US10922227B2Feb 16, 2021

Resource-specific flushes and invalidations of cache and memory fabric structures

INTEL CORP0 citations62
US10521876B2Dec 31, 2019

Deferred geometry rasterization technology

INTEL CORP1 citations62
US10853995B2Dec 1, 2020

Physically based shading via fixed-functionality shader libraries

INTEL CORP0 citations52
US10706612B2Jul 7, 2020

Tile-based immediate mode rendering with early hierarchical-z

INTEL CORP0 citations52
US10672366B2Jun 2, 2020

Handling surface level coherency without reliance on fencing

INTEL CORP0 citations52
US10452552B2Oct 22, 2019

Memory-based dependency tracking and cache pre-fetch hardware for multi-resolution shading

INTEL CORP0 citations52
US10373365B2Aug 6, 2019

Topology shader technology

INTEL CORP0 citations52
US10347039B2Jul 9, 2019

Physically based shading via fixed-functionality shader libraries

INTEL CORP0 citations52

SALVI MARCO

1 patent

KOKER ALTUG

1 patent

LAURITZEN ANDREW T

1 patent