Inventor

TIEN LI-CHUN

TW256 patents

⚠️ This page may combine multiple inventors who share the name “TIEN LI-CHUN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TIEN LI-CHUN

TAIWAN SEMICONDUCTOR MFG CO LTD

Semiconductor device including standard cells having different cell height

Integrated circuit and method of forming an integrated circuit

Integrated circuit and method of forming an integrated circuit

Cell of transmission gate free circuit and integrated circuit and integrated circuit layout including the same

Method and apparatus for forming an integrated circuit with a metalized resistor in a standard cell configuration

System and method of processing cutting layout and example switching circuit

Multi-patterning conflict free integrated circuit design

Cell structure with intermediate metal layers for power supplies

Integrated circuit and manufacturing method thereof

Transmission gate structure and method

Method for generating layout diagram including cell having pin patterns and semiconductor device based on same

Semiconductor device including standard cells

Integrated circuit layout method, device, and system

Double height cell regions, semiconductor device having the same, and method of generating a layout diagram corresponding to the same

Engineering change order cell structure having always-on transistor

Integrated circuit layout method and device

Integrated circuit, system for and method of forming an integrated circuit

Cell of transmission gate free circuit and integrated circuit layout including the same

Semiconductor device having engineering change order (ECO) cells and method of using

Method of generating engineering change order (ECO) layout of base cell and computer-readable medium comprising executable instructions for carrying out said method

Method of forming layout design

Connecting techniques for stacked CMOS devices

System and method of layout design for integrated circuits

Non-hierarchical metal layers for integrated circuits

Method and system of layout placement based on multilayer gridlines

Connecting techniques for stacked CMOS devices

Semiconductor device and method of manufacturing semiconductor device

Cell layout design and method

Semiconductor structure

Integrated circuit having a high cell density

Circuits and structures including tap cells and fabrication methods thereof

Fuse structure

TAIWAN SEMICONDUCTOR MFG

Method for automatically modifying integrated circuit layout

Masks formed based on integrated circuit layout design having standard cell that includes extended active region

Method for reducing layers revision in engineering change order

Standard cell without OD space effect in Y-direction

Layout architecture for improving circuit performance

Transistor layout for standard cell with optimized mechanical stress effect

Method of forming layout design

Masks formed based on integrated circuit layout design having cell that includes extended active region

Integrated circuit

Multiple via connections using connectivity rings

HOU YUNG-CHIN

Integrated circuit layouts with power rails under bottom metal layer

Standard cells having flexible layout architecture/boundaries

LU LEE-CHUNG

Non-hierarchical metal layers for integrated circuits

Methods for cell boundary isolation in double patterning design

CHERN CHAN-HONG

Systems and methods of designing integrated circuits

CHEN HUANG-YU

Method and apparatus for achieving multiple patterning technology compliant design layout

OU TSONG-HUA

Adaptive fin design for FinFETs

CHEN KUO-JI

Adding decoupling function for tap cells