Inventor
QIU XIAOGANG
US23 patents
⚠️ This page may combine multiple inventors who share the name “QIU XIAOGANG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
NVIDIA CORP
13 patentsUS11080051B2Aug 3, 2021
Techniques for efficiently transferring data to a processor
NVIDIA CORP9 citations85
US9471307B2Oct 18, 2016
System and processor that include an implementation of decoupled pipelines
NVIDIA CORP10 citations81
US11803380B2Oct 31, 2023
High performance synchronization mechanisms for coordinating operations on a computer system
NVIDIA CORP2 citations71
US10459861B2Oct 29, 2019
Unified cache for diverse memory traffic
NVIDIA CORP2 citations71
US9971699B2May 15, 2018
Method to control cache replacement for decoupled data fetch
NVIDIA CORP2 citations71
US9612836B2Apr 4, 2017
System, method, and computer program product for implementing software-based scoreboarding
NVIDIA CORP5 citations71
US9477482B2Oct 25, 2016
System, method, and computer program product for implementing multi-cycle register file bypass
NVIDIA CORP4 citations69
US11907717B2Feb 20, 2024
Techniques for efficiently transferring data to a processor
NVIDIA CORP0 citations62
US11604649B2Mar 14, 2023
Techniques for efficiently transferring data to a processor
NVIDIA CORP0 citations62
US11347668B2May 31, 2022
Unified cache for diverse memory traffic
NVIDIA CORP0 citations60
US9798544B2Oct 24, 2017
Reordering buffer for memory access locality
NVIDIA CORP0 citations51
US10705994B2Jul 7, 2020
Unified cache for diverse memory traffic
NVIDIA CORP0 citations50
US10489200B2Nov 26, 2019
Hierarchical staging areas for scheduling threads for execution
NVIDIA CORP0 citations41
QIU XIAOGANG
3 patentsUS7484039B2Jan 27, 2009
Method and apparatus for implementing a grid storage system
QIU XIAOGANG7 citations64
US8533435B2Sep 10, 2013
Reordering operands assigned to each one of read request ports concurrently accessing multibank register file to avoid bank conflict
QIU XIAOGANG4 citations61
US10255228B2Apr 9, 2019
System and method for performing shaped memory access operations
QIU XIAOGANG1 citations52