P

Inventor

GIROUX OLIVIER

US42 patents
⚠️ This page may combine multiple inventors who share the name “GIROUX OLIVIER”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NVIDIA CORP

34 patents
US11080051B2Aug 3, 2021

Techniques for efficiently transferring data to a processor

NVIDIA CORP9 citations85
US10977037B2Apr 13, 2021

Techniques for comprehensively synchronizing execution threads

NVIDIA CORP5 citations83
US9471307B2Oct 18, 2016

System and processor that include an implementation of decoupled pipelines

NVIDIA CORP10 citations81
US9830224B2Nov 28, 2017

Selective fault stalling for a GPU memory pipeline in a unified virtual memory system

NVIDIA CORP4 citations73
US11803380B2Oct 31, 2023

High performance synchronization mechanisms for coordinating operations on a computer system

NVIDIA CORP2 citations71
US9612836B2Apr 4, 2017

System, method, and computer program product for implementing software-based scoreboarding

NVIDIA CORP5 citations71
US9459876B2Oct 4, 2016

System, method, and computer program product for managing divergences and synchronization points during thread block execution by using a double sided queue for token storage

NVIDIA CORP4 citations70
US10769076B2Sep 8, 2020

Distributed address translation in a multi-node interconnect fabric

NVIDIA CORP3 citations69
US10067768B2Sep 4, 2018

Execution of divergent threads using a convergence barrier

NVIDIA CORP2 citations69
US12499052B2Dec 16, 2025

Method and apparatus for efficient access to multidimensional data structures and/or other large data blocks

NVIDIA CORP1 citations62
US11907717B2Feb 20, 2024

Techniques for efficiently transferring data to a processor

NVIDIA CORP0 citations62
US11604649B2Mar 14, 2023

Techniques for efficiently transferring data to a processor

NVIDIA CORP0 citations62
US8949841B2Feb 3, 2015

Approach for a configurable phase-based priority scheduler

NVIDIA CORP3 citations62
US11061741B2Jul 13, 2021

Techniques for efficiently performing data reductions in parallel processing units

NVIDIA CORP0 citations61
US11016802B2May 25, 2021

Techniques for ordering atomic operations

NVIDIA CORP1 citations61
US12517730B2Jan 6, 2026

Self-synchronizing remote memory operations in a data center or multiprocessor system

NVIDIA CORP0 citations59
US12474835B2Nov 18, 2025

Self-synchronizing remote memory operations in a multiprocessor system

NVIDIA CORP0 citations59
US12105960B2Oct 1, 2024

Self-synchronizing remote memory operations in a multiprocessor system

NVIDIA CORP0 citations59
US11327900B2May 10, 2022

Securing memory accesses in a virtualized environment

NVIDIA CORP0 citations59
US12333311B2Jun 17, 2025

Cooperative group arrays

NVIDIA CORP0 citations57
US12248788B2Mar 11, 2025

Distributed shared memory

NVIDIA CORP0 citations57
US11847508B2Dec 19, 2023

Convergence among concurrently executing threads

NVIDIA CORP0 citations57
US12450683B2Oct 21, 2025

Application programming interface to provide information

NVIDIA CORP0 citations55
US12405801B2Sep 2, 2025

Scalarization of instructions for SIMT architectures

NVIDIA CORP0 citations55
US10817295B2Oct 27, 2020

Thread-level sleep in a multithreaded architecture

NVIDIA CORP0 citations51
US10437593B2Oct 8, 2019

Techniques for comprehensively synchronizing execution threads

NVIDIA CORP0 citations51
US10346212B2Jul 9, 2019

Approach for a configurable phase-based priority scheduler

NVIDIA CORP0 citations51
US10255075B2Apr 9, 2019

System, method, and computer program product for managing out-of-order execution of program instructions

NVIDIA CORP0 citations51
US9798544B2Oct 24, 2017

Reordering buffer for memory access locality

NVIDIA CORP0 citations51
US12340259B2Jun 24, 2025

Thread synchronization across memory synchronization domains

NVIDIA CORP0 citations48
US12536056B2Jan 27, 2026

Hardware accelerated synchronization with asynchronous transaction support

NVIDIA CORP0 citations47
US12271765B2Apr 8, 2025

Techniques for efficiently synchronizing multiple program threads

NVIDIA CORP0 citations44
US10489200B2Nov 26, 2019

Hierarchical staging areas for scheduling threads for execution

NVIDIA CORP0 citations41
US9477480B2Oct 25, 2016

System and processor for implementing interruptible batches of instructions

NVIDIA CORP0 citations41

CHOQUETTE JACK HILAIRE

2 patents

NELSON PETER MICHAEL

1 patent

GIROUX OLIVIER

1 patent

MCCORMACK JOEL JAMES

1 patent

CHOQUETTE JACK

1 patent

FETTERMAN MICHAEL

1 patent

MICHELIN & CIE

1 patent