Inventor
ALUR SIDDHARTH K
US19 patents
Patents
19 patentsUS10424530B1Sep 24, 2019
Electrical interconnections with improved compliance due to stress relaxation and method of making
INTEL CORP28 citations93
US10020262B2Jul 10, 2018
High resolution solder resist material for silicon bridge application
INTEL CORP7 citations83
US11158558B2Oct 26, 2021
Package with underfill containment barrier
INTEL CORP5 citations82
US11664290B2May 30, 2023
Package with underfill containment barrier
INTEL CORP3 citations71
US10741947B2Aug 11, 2020
Plated through hole socketing coupled to a solder ball to engage with a pin
INTEL CORP2 citations71
US10685850B2Jun 16, 2020
High density organic interconnect structures
INTEL CORP3 citations71
US10903137B2Jan 26, 2021
Electrical interconnections with improved compliance due to stress relaxation and method of making
INTEL CORP0 citations62
US12327773B2Jun 10, 2025
Package with underfill containment barrier
INTEL CORP0 citations61
US12062551B2Aug 13, 2024
High density organic interconnect structures
INTEL CORP0 citations61
US11935805B2Mar 19, 2024
Package with underfill containment barrier
INTEL CORP0 citations61
US11631595B2Apr 18, 2023
High density organic interconnect structures
INTEL CORP0 citations61
US11195727B2Dec 7, 2021
High density organic interconnect structures
INTEL CORP0 citations61
US11075130B2Jul 27, 2021
Package substrate having polymer-derived ceramic core
INTEL CORP0 citations58
US10727184B2Jul 28, 2020
Microelectronic device including non-homogeneous build-up dielectric
INTEL CORP0 citations51
US11393762B2Jul 19, 2022
Formation of tall metal pillars using multiple photoresist layers
INTEL CORP0 citations50
US10553453B2Feb 4, 2020
Systems and methods for semiconductor packages using photoimageable layers
INTEL CORP0 citations48
US9728500B2Aug 8, 2017
Integrated circuit surface layer with adhesion-functional group
INTEL CORP0 citations47
US12224253B2Feb 11, 2025
Magnetic inductor device and method
INTEL CORP0 citations43
US10384431B2Aug 20, 2019
Methods for forming a substrate structure for an electrical component and an apparatus for applying pressure to an electrically insulating laminate located on a core substrate
INTEL CORP0 citations41