Inventor
JEN WEI-LUN K
US11 patents
⚠️ This page may combine multiple inventors who share the name “JEN WEI-LUN K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
10 patentsUS10020262B2Jul 10, 2018
High resolution solder resist material for silicon bridge application
INTEL CORP7 citations83
US11158558B2Oct 26, 2021
Package with underfill containment barrier
INTEL CORP5 citations82
US11581271B2Feb 14, 2023
Methods to pattern TFC and incorporation in the ODI architecture and in any build up layer of organic substrate
INTEL CORP2 citations72
US11443970B2Sep 13, 2022
Methods of forming a package substrate
INTEL CORP1 citations72
US10629469B2Apr 21, 2020
Solder resist layers for coreless packages and methods of fabrication
INTEL CORP4 citations72
US11664290B2May 30, 2023
Package with underfill containment barrier
INTEL CORP3 citations71
US12327773B2Jun 10, 2025
Package with underfill containment barrier
INTEL CORP0 citations61
US12068172B2Aug 20, 2024
Sacrificial pads to prevent galvanic corrosion of FLI bumps in EMIB packages
INTEL CORP0 citations61
US11935805B2Mar 19, 2024
Package with underfill containment barrier
INTEL CORP0 citations61
US11552019B2Jan 10, 2023
Substrate patch reconstitution options
INTEL CORP1 citations60