Inventor
CHAVALI SRI CHAITRA J
US14 patents
Patents
14 patentsUS11430724B2Aug 30, 2022
Ultra-thin, hyper-density semiconductor packages
INTEL CORP5 citations83
US9837341B1Dec 5, 2017
Tin-zinc microbump structures
INTEL CORP6 citations83
US11158558B2Oct 26, 2021
Package with underfill containment barrier
INTEL CORP5 citations82
US11355849B2Jun 7, 2022
Antenna package using ball attach array to connect antenna and base substrates
INTEL CORP4 citations73
US11664290B2May 30, 2023
Package with underfill containment barrier
INTEL CORP3 citations71
US12476174B2Nov 18, 2025
Ultra-thin, hyper-density semiconductor packages
INTEL CORP0 citations62
US12406914B2Sep 2, 2025
Ultra-thin, hyper-density semiconductor packages
INTEL CORP0 citations62
US12327773B2Jun 10, 2025
Package with underfill containment barrier
INTEL CORP0 citations61
US11935805B2Mar 19, 2024
Package with underfill containment barrier
INTEL CORP0 citations61
US10373900B2Aug 6, 2019
Tin-zinc microbump structures and method of making same
INTEL CORP0 citations51
US11393762B2Jul 19, 2022
Formation of tall metal pillars using multiple photoresist layers
INTEL CORP0 citations50
US11222877B2Jan 11, 2022
Thermally coupled package-on-package semiconductor packages
INTEL CORP0 citations47
US9728500B2Aug 8, 2017
Integrated circuit surface layer with adhesion-functional group
INTEL CORP0 citations47
US10384431B2Aug 20, 2019
Methods for forming a substrate structure for an electrical component and an apparatus for applying pressure to an electrically insulating laminate located on a core substrate
INTEL CORP0 citations41