Inventor
ALUR AMRUTHAVALLI P
US18 patents
⚠️ This page may combine multiple inventors who share the name “ALUR AMRUTHAVALLI P”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
16 patentsUS7749900B2Jul 6, 2010
Method and core materials for semiconductor packaging
INTEL CORP26 citations92
US11158558B2Oct 26, 2021
Package with underfill containment barrier
INTEL CORP5 citations82
US11328968B2May 10, 2022
Stacked die cavity package
INTEL CORP2 citations73
US11581271B2Feb 14, 2023
Methods to pattern TFC and incorporation in the ODI architecture and in any build up layer of organic substrate
INTEL CORP2 citations72
US11664290B2May 30, 2023
Package with underfill containment barrier
INTEL CORP3 citations71
US11955426B2Apr 9, 2024
Package-integrated multi-turn coil embedded in a package magnetic core
INTEL CORP0 citations62
US11705377B2Jul 18, 2023
Stacked die cavity package
INTEL CORP0 citations62
US11404364B2Aug 2, 2022
Multi-layer embedded magnetic inductor coil
INTEL CORP0 citations62
US11393751B2Jul 19, 2022
Package-integrated multi-turn coil embedded in a package magnetic core
INTEL CORP1 citations62
US12327773B2Jun 10, 2025
Package with underfill containment barrier
INTEL CORP0 citations61
US11935805B2Mar 19, 2024
Package with underfill containment barrier
INTEL CORP0 citations61
US11552019B2Jan 10, 2023
Substrate patch reconstitution options
INTEL CORP1 citations60
US11272619B2Mar 8, 2022
Apparatus with embedded fine line space in a cavity, and a method for forming the same
INTEL CORP0 citations59
US10494700B2Dec 3, 2019
Method of fabricating a microelectronic substrate
INTEL CORP0 citations51
US9758845B2Sep 12, 2017
Microelectronic substrates having copper alloy conductive route structures
INTEL CORP0 citations51
US7909977B2Mar 22, 2011
Method of manufacturing a substrate for a microelectronic device, and substrate formed thereby
INTEL CORP1 citations51