Inventor
WU TERESA J
US6 patents
Patents
6 patentsUS6294449B1Sep 25, 2001
Self-aligned contact for closely spaced transistors
IBM37 citations92
US6429067B1Aug 6, 2002
Dual mask process for semiconductor devices
IBM15 citations81
US6303275B1Oct 16, 2001
Method for resist filling and planarization of high aspect ratio features
IBM7 citations72
US12349445B2Jul 1, 2025
Vertically integrated semiconductor device
IBM0 citations62
US12142599B2Nov 12, 2024
Stacked transistor structure with reflection layer
IBM0 citations62
US7111257B2Sep 19, 2006
Using a partial metal level mask for early test results
IBM5 citations60