Inventor
BANG KYONG-MO
US27 patents
⚠️ This page may combine multiple inventors who share the name “BANG KYONG-MO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INVENSAS CORP
18 patentsUS9349707B1May 24, 2016
Contact arrangements for stackable microelectronic package structures with multiple ranks
INVENSAS CORP29 citations94
US9484080B1Nov 1, 2016
High-bandwidth memory application with controlled impedance loading
INVENSAS CORP8 citations84
US9425167B2Aug 23, 2016
Stackable microelectronic package structures
INVENSAS CORP5 citations84
US8980693B2Mar 17, 2015
Stackable microelectronic package structures
INVENSAS CORP4 citations84
US10566310B2Feb 18, 2020
Microelectronic packages having stacked die and wire bond interconnects
INVENSAS CORP2 citations73
US9928883B2Mar 27, 2018
TFD I/O partition for high-speed, high-density applications
INVENSAS CORP2 citations73
US9337170B1May 10, 2016
Contact arrangements for stackable microelectronic package structures
INVENSAS CORP3 citations73
US10008469B2Jun 26, 2018
Wafer-level packaging using wire bond wires in place of a redistribution layer
INVENSAS CORP4 citations72
US9847238B2Dec 19, 2017
Fan-out wafer-level packaging using metal foil lamination
INVENSAS CORP3 citations72
US9543277B1Jan 10, 2017
Wafer level packages with mechanically decoupled fan-in and fan-out areas
INVENSAS CORP3 citations72
US10468380B2Nov 5, 2019
Stackable microelectronic package structures
INVENSAS CORP0 citations52
US10026467B2Jul 17, 2018
High-bandwidth memory application with controlled impedance loading
INVENSAS CORP0 citations52
US9911717B2Mar 6, 2018
Stackable microelectronic package structures
INVENSAS CORP0 citations52
US9679613B1Jun 13, 2017
TFD I/O partition for high-speed, high-density applications
INVENSAS CORP1 citations52
US9281296B2Mar 8, 2016
Die stacking techniques in BGA memory package for small footprint CPU and memory motherboard design
INVENSAS CORP1 citations52
US9646946B2May 9, 2017
Fan-out wafer-level packaging using metal foil lamination
INVENSAS CORP1 citations51
US9502372B1Nov 22, 2016
Wafer-level packaging using wire bond wires in place of a redistribution layer
INVENSAS CORP0 citations51
US9343398B2May 17, 2016
BGA ballout partition techniques for simplified layout in motherboard with multiple power supply rail
INVENSAS CORP0 citations42
TESSERA INC
4 patentsUS7294928B2Nov 13, 2007
Components, methods and assemblies for stacked packages
TESSERA INC151 citations98
US7246431B2Jul 24, 2007
Methods of making microelectronic packages including folded substrates
TESSERA INC101 citations98
US7053485B2May 30, 2006
Microelectronic packages with self-aligning features
TESSERA INC76 citations98
US7935569B2May 3, 2011
Components, methods and assemblies for stacked packages
TESSERA INC7 citations83
ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC
4 patentsUS12322677B1Jun 3, 2025
Fluid channel geometry optimizations to improve cooling efficiency
ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC1 citations63
US12341083B2Jun 24, 2025
Electronic device cooling structures bonded to semiconductor elements
ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC0 citations62
US12191234B2Jan 7, 2025
Integrated cooling assemblies for advanced device packaging and methods of manufacturing the same
ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC0 citations62
US12525506B2Jan 13, 2026
Embedded cooling systems for advanced device packaging and methods of manufacturing the same
ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC0 citations60