Inventor
CHARAGULLA SANJAY K
US9 patents
Patents
9 patentsUS7417452B1Aug 26, 2008
Techniques for providing adjustable on-chip termination impedance
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US7378868B2May 27, 2008
Modular I/O bank architecture
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US7664978B2Feb 16, 2010
Memory interface circuitry with phase detection
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US7490209B1Feb 10, 2009
Fully buffered DIMM system and method with hard-IP memory controller and soft-IP frequency controller
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US7555667B1Jun 30, 2009
Programmable logic device integrated circuit with dynamic phase alignment capabilities and shared phase-locked-loop circuitry
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US7282973B1Oct 16, 2007
Enhanced DLL phase output scheme
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US7031222B1Apr 18, 2006
DQS postamble filtering
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US7825682B1Nov 2, 2010
Techniques for providing adjustable on-chip termination impedance
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US7324405B1Jan 29, 2008
DQS postamble filtering
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