Inventor

YANG JENG-WEI

TW28 patents

Patents

28 patents

US9887206B2Feb 6, 2018

Method of making split gate non-volatile memory cell with 3D FinFET structure

SILICON STORAGE TECH INC56 citations98

US9276006B1Mar 1, 2016

Split gate non-volatile flash memory cell having metal-enhanced gates and method of making same

SILICON STORAGE TECH INC48 citations94

US10714634B2Jul 14, 2020

Non-volatile split gate memory cells with integrated high K metal control gates and method of making same

SILICON STORAGE TECH INC7 citations84

US10418451B1Sep 17, 2019

Split-gate flash memory cell with varying insulation gate oxides, and method of forming same

SILICON STORAGE TECH INC9 citations84

US10249631B2Apr 2, 2019

Split gate non-volatile flash memory cell having metal gates

SILICON STORAGE TECH INC7 citations84

US9985042B2May 29, 2018

Method of integrating FinFET CMOS devices with embedded nonvolatile memory cells

SILICON STORAGE TECH INC14 citations84

US9972630B2May 15, 2018

Split gate non-volatile flash memory cell having metal gates and method of making same

SILICON STORAGE TECH INC14 citations84

US9793281B2Oct 17, 2017

Non-volatile split gate memory cells with integrated high K metal gate logic device and metal-free erase gate, and method of making same

SILICON STORAGE TECH INC7 citations84

US9721958B2Aug 1, 2017

Method of forming self-aligned split-gate memory cell array with metal gates and logic devices

SILICON STORAGE TECH INC7 citations84

US9634018B2Apr 25, 2017

Split gate non-volatile memory cell with 3D finFET structure, and method of making same

SILICON STORAGE TECH INC12 citations84

US9634019B1Apr 25, 2017

Non-volatile split gate memory cells with integrated high K metal gate, and method of making same

SILICON STORAGE TECH INC14 citations84

US9496369B2Nov 15, 2016

Method of forming split-gate memory cell array along with low and high voltage logic devices

SILICON STORAGE TECH INC16 citations84

US9431407B2Aug 30, 2016

Method of making embedded memory device with silicon-on-insulator substrate

SILICON STORAGE TECH INC10 citations84

US9379121B1Jun 28, 2016

Split gate non-volatile flash memory cell having metal gates and method of making same

SILICON STORAGE TECH INC16 citations84

US9484261B2Nov 1, 2016

Formation of self-aligned source for split-gate non-volatile memory cell

SILICON STORAGE TECH INC10 citations82

US10608090B2Mar 31, 2020

Method of manufacturing a split-gate flash memory cell with erase gate

SILICON STORAGE TECH INC6 citations73

US10312246B2Jun 4, 2019

Split-gate flash memory cell with improved scaling using enhanced lateral control gate to floating gate coupling

SILICON STORAGE TECH INC2 citations73

US9972493B2May 15, 2018

Method of forming low height split gate memory cells

SILICON STORAGE TECH INC2 citations73

US9793279B2Oct 17, 2017

Split gate non-volatile memory cell having a floating gate, word line, erase gate, and method of manufacturing

SILICON STORAGE TECH INC2 citations73

US9793280B2Oct 17, 2017

Double patterning method of forming semiconductor active areas and isolation regions

SILICON STORAGE TECH INC2 citations63

US7358559B2Apr 15, 2008

Bi-directional read/program non-volatile floating gate memory array, and method of formation

SILICON STORAGE TECH INC3 citations63

US11315636B2Apr 26, 2022

Four gate, split-gate flash memory array with byte erase operation

SILICON STORAGE TECH INC1 citations57

US10381359B2Aug 13, 2019

Non-volatile split game memory cells with integrated high K metal gate logic device and metal-free erase gate, and method of making same

SILICON STORAGE TECH INC0 citations52

US10141321B2Nov 27, 2018

Method of forming flash memory with separate wordline and erase gates

SILICON STORAGE TECH INC1 citations52

US11488970B2Nov 1, 2022

Method of forming split gate memory cells with thinner tunnel oxide

SILICON STORAGE TECH INC0 citations47

YANG JENG-WEI

Patents

Method of making split gate non-volatile memory cell with 3D FinFET structure

Split gate non-volatile flash memory cell having metal-enhanced gates and method of making same

Non-volatile split gate memory cells with integrated high K metal control gates and method of making same

Split-gate flash memory cell with varying insulation gate oxides, and method of forming same

Split gate non-volatile flash memory cell having metal gates

Method of integrating FinFET CMOS devices with embedded nonvolatile memory cells

Split gate non-volatile flash memory cell having metal gates and method of making same

Non-volatile split gate memory cells with integrated high K metal gate logic device and metal-free erase gate, and method of making same

Method of forming self-aligned split-gate memory cell array with metal gates and logic devices

Split gate non-volatile memory cell with 3D finFET structure, and method of making same

Non-volatile split gate memory cells with integrated high K metal gate, and method of making same

Method of forming split-gate memory cell array along with low and high voltage logic devices

Method of making embedded memory device with silicon-on-insulator substrate

Split gate non-volatile flash memory cell having metal gates and method of making same

Formation of self-aligned source for split-gate non-volatile memory cell

Method of manufacturing a split-gate flash memory cell with erase gate

Split-gate flash memory cell with improved scaling using enhanced lateral control gate to floating gate coupling

Method of forming low height split gate memory cells

Split gate non-volatile memory cell having a floating gate, word line, erase gate, and method of manufacturing

Integration of split gate flash memory array and logic devices

Self-aligned source for split-gate non-volatile memory cell

Split-gate flash memory array with byte erase operation

Double patterning method of forming semiconductor active areas and isolation regions

Bi-directional read/program non-volatile floating gate memory array, and method of formation

Four gate, split-gate flash memory array with byte erase operation

Non-volatile split game memory cells with integrated high K metal gate logic device and metal-free erase gate, and method of making same

Method of forming flash memory with separate wordline and erase gates

Method of forming split gate memory cells with thinner tunnel oxide