Inventor

SU CHIEN-SHENG

US39 patents

⚠️ This page may combine multiple inventors who share the name “SU CHIEN-SHENG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SU CHIEN-SHENG

SILICON STORAGE TECH INC

Method of making split gate non-volatile memory cell with 3D FinFET structure

Split gate non-volatile flash memory cell having a floating gate, control gate, select gate and an erase gate with an overhang over the floating gate, array and method of manufacturing

Split gate non-volatile flash memory cell having a floating gate, control gate, select gate and an erase gate with an overhang over the floating gate, array and method of manufacturing

Split gate non-volatile flash memory cell having metal-enhanced gates and method of making same

Self aligned method of forming a semiconductor array of non-volatile memory cells

Non-volatile split gate memory cells with integrated high K metal control gates and method of making same

Split-gate flash memory cell with varying insulation gate oxides, and method of forming same

Split gate non-volatile flash memory cell having metal gates

Method of forming pairs of three-gate non-volatile flash memory cells using two polysilicon deposition steps

Method of integrating FinFET CMOS devices with embedded nonvolatile memory cells

Split gate non-volatile flash memory cell having metal gates and method of making same

Non-volatile split gate memory cells with integrated high K metal gate logic device and metal-free erase gate, and method of making same

Method of forming self-aligned split-gate memory cell array with metal gates and logic devices

Non-volatile split gate memory cells with integrated high K metal gate, and method of making same

Split gate non-volatile memory cell with 3D finFET structure, and method of making same

Method of forming split-gate memory cell array along with low and high voltage logic devices

Method of making embedded memory device with silicon-on-insulator substrate

Split gate non-volatile flash memory cell having metal gates and method of making same

Split gate non-volatile flash memory cell having a silicon-metal floating gate and method of making same

Formation of self-aligned source for split-gate non-volatile memory cell

Split-gate flash memory cell with improved scaling using enhanced lateral control gate to floating gate coupling

Method of forming low height split gate memory cells

Integration of split gate flash memory array and logic devices

Split gate non-volatile memory cell having a floating gate, word line, erase gate, and method of manufacturing

Method of forming memory array and logic devices

Method of making embedded memory device with silicon-on-insulator substrate

Self-aligned source for split-gate non-volatile memory cell

Method of forming a three-gate non-volatile flash memory cell using two polysilicon deposition steps

Double patterning method of forming semiconductor active areas and isolation regions

Non-volatile split game memory cells with integrated high K metal gate logic device and metal-free erase gate, and method of making same

Method of forming flash memory with separate wordline and erase gates

Non-volatile memory cells with enhanced channel region effective width, and method of making same

EON SILICON DEVICES INC

Method and apparatus for measuring the threshold voltage of flash EEPROM memory cells being applied a variable control gate bias

Method of erasing a flash EEPROM memory

Method of achieving narrow VT distribution after erase in flash EEPROM

SEEQ TECHNOLOGY INC

Block electrically erasable EEPROM

KOTOV ALEXANDER

Non-volatile memory cell having a high K dielectric and metal gate

LIU XIAN

Method of forming a memory cell by reducing diffusion of dopants under a gate

TOREN WILLEM-JAN

Self-aligned stack gate structure for use in a non-volatile memory array and a method of forming such structure