Inventor

RIOS RAFAEL

US163 patents

⚠️ This page may combine multiple inventors who share the name “RIOS RAFAEL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

RIOS RAFAEL

INTEL CORP

Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication

Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication

N-gate transistor

Integration methods to fabricate internal spacers for nanowire devices

Isolated tri-gate transistor fabricated on bulk substrate

Integrated circuit with dynamic threshold voltage

CMOS nanowire structure

Silicon and silicon germanium nanowire structures

Semiconductor device with isolated body portion

Fabrication of non-planar IGZO devices for improved electrostatics

Threshold switching selector based memory

High mobility asymmetric field effect transistors with a band-offset semiconductor drain spacer

Systems, methods, and apparatuses for implementing a high mobility low contact resistance semiconducting oxide in metal contact vias for thin film transistors

Integration methods to fabricate internal spacers for nanowire devices

Dielectric metal oxide cap for channel containing germanium

Stackable thin film memory

Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs

Leakage reduction structures for nanowire transistors

Offstate parasitic leakage reduction for tunneling field effect transistors

Vertical shared gate thin-film transistor-based charge storage memory

KEPLER COMPUTING INC

Ferroelectric or paraelectric based sequential circuit

Majority logic gate with non-linear input capacitors

Multi-function threshold gate with adaptive threshold and stacked planar paraelectric capacitors

Parallel pull-up and pull-down networks controlled asynchronously by majority gate or minority gate logic

Reset mechanism for a chain of majority or minority gates having paraelectric material

Majority logic gate having paraelectric input capacitors and a local conditioning mechanism

Majority logic gate with non-linear input capacitors and conditioning logic

Multi-function linear threshold gate with input based adaptive threshold

Method of fabricating transistors and stacked planar capacitors for memory and logic applications

Reset mechanism for an adder or a multiplier having paraelectric material

Low power multiplier with non-linear polar material based reset mechanism with sequential reset

Majority or minority logic gate with non-linear input capacitors without reset

Non-linear polar material based low power multiplier with NOR and NAND gate based reset mechanism

Method of adjusting threshold of a ferroelectric capacitive-input circuit

Majority logic gate having ferroelectric input capacitors and a pulsing scheme coupled to a conditioning logic

Multi-function threshold gate with adaptive threshold and stacked planar ferroelectric capacitors

KIM SEIYON

Integration methods to fabricate internal spacers for nanowire devices

CMOS nanowire structure

CMOS nanowire structure

CAPPELLANI ANNALISA

Semiconductor device with isolated body portion

Semiconductor devices having modulated nanowire counts

Isolated and bulk semiconductor devices formed on a same bulk substrate

KUHN KELIN J

Silicon and silicon germanium nanowire structures

Silicon and silicon germanium nanowire structures

CEA STEPHEN M

Nanowire structures having non-discrete source and drain regions

Nanowire structures having non-discrete source and drain regions

HARELAND SCOTT A

Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication

KOTLYAR ROZA

Tunneling field effect transistors (TFETs) for CMOS approaches to fabricating N-type and P-type TFETs

GILES MARTIN D

Semiconductor device having metallic source and drain regions

GOOGLE LLC

Non-planar semiconductor device having hybrid geometry-based active region